MPC9352 datasheet(5/16 Pages) MOTOROLA

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MPC9352

TIMING SOLUTIONS

MOTOROLA

Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C)a

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input reference frequency in PLL modeb

÷4 feedback

÷6 feedback

÷8 feedback

÷12 feedback

Input reference frequency in PLL bypass modec

50.0

33.3

25.0

16.67

100.0

66.6

50.0

33.3

250.0

MHz

fVCO

VCO lock frequency ranged

200

400

MHz

fMAX

Output Frequency

÷2 outpute

÷4 output

÷6 output

÷8 output

÷12 output

100

33.3

16.67

200

100

66.6

33.3

MHz

frefDC

Reference Input Duty Cycle

tr, tf

CCLK Input Rise/Fall Time

1.0

0.8 to 2.0V

t(∅)

Propagation Delay CCLK to FB_IN

fref > 40 MHz

(static phase offset)

fref < 40 MHz

-50

-200

+150

PLL locked

tsk(O)

Output-to-output Skewf

all outputs, any frequency

within QA output bank

within QB output bank

within QC output bank

200

100

Output duty cycle

tr, tf

Output Rise/Fall Time

0.1

1.0

0.55 to 2.4V

tPLZ, HZ

Output Disable Time

tPZL, LZ

Output Enable Time

tJIT(CC)

Cycle-to-cycle jitter

output frequencies mixed

outputs are in any

÷4 and ÷6 combination

all outputs same frequency

400

250

100

tJIT(PER)

Period Jitter

output frequencies mixed

outputs are in any

÷4 and ÷6 combination

all outputs same frequency

200

150

tJIT(∅)

I/O Phase Jitter

÷4 feedback divider RMS (1 σ)g

÷6 feedback divider RMS (1 σ)

÷8 feedback divider RMS (1 σ)

÷12 feedback divider RMS (1 σ)

18 - 20

PLL closed loop bandwidthh

÷4 feedback

÷6 feedback

÷8 feedback

÷12 feedback

3.0 - 10.0

1.5 - 6.0

1.0 - 3.5

0.5 - 2.0

MHz

tLOCK

Maximum PLL Lock Time

AC characteristics apply for parallel output termination of 50

Ω to VTT.

PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a

÷2 divider for feedback.

In PLL bypass mode, the MPC9352 divides the input reference clock.

The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.

See Table 9 and Table 10 for output divider configurations.

See application section for part-to-part skew calculation.

See application section for a jitter calculation for other confidence factors than 1

-3 dB point of PLL transfer characteristics.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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