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ADAU1977WBCPZ-R7 Datasheet(PDF) 8 Page - Analog Devices |
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ADAU1977WBCPZ-R7 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 68 page  ADAU1977 Data Sheet Rev. C | Page 8 of 68 TIMING SPECIFICATIONS Table 6. Limit at Parameter Min Max Unit Description INPUT MASTER CLOCK (MCLK) Duty Cycle 40 60 % MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS fMCLK See Table 10 MHz MCLKIN frequency, PLL in MCLK mode RESET Reset Pulse 15 ns RST low PLL Lock Time 10 ms I2C PORT fSCL 400 kHz SCL frequency tSCLH 0.6 µs SCL high tSCLL 1.3 µs SCL low tSCS 0.6 µs Setup time; relevant for repeated start condition tSCH 0.6 µs Hold time; after this period of time, the first clock pulse is generated tDS 100 ns Data setup time tDH 0 Data hold time tSCR 300 ns SCL rise time tSCF 300 ns SCL fall time tSDR 300 ns SDA rise time tSDF 300 ns SDA fall time tBFT 1.3 µs Bus-free time; time between stop and start tSUSTO 0.6 µs Setup time for stop condition SPI PORT tCCPH 35 ns CCLK high tCCPL 35 ns CCLK low fCCLK 10 MHz CCLK frequency tCDS 10 ns CIN setup to CCLK rising tCDH 10 ns CIN hold from CCLK rising tCLS 10 ns CLATCH setup to CCLK rising tCLH 40 ns CLATCH hold from CCLK rising tCLPH 10 ns CLATCH high tCOE 30 ns COUT enable from CLATCH falling tCOD 30 ns COUT delay from CCLK falling tCOTS 30 ns COUT tristate from CLATCH rising ADC SERIAL PORT tABH 10 ns BCLK high, slave mode tABL 10 ns BCLK low, slave mode tALS 10 ns LRCLK setup to BCLK rising, slave mode tALH 5 ns LRCLK hold from BCLK rising, slave mode tABDD 18 ns SDATAOUTx delay from BCLK falling |
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