ADAU1977WBCPZ-R7 datasheet(22/68 Pages) AD

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ADAU1977

Data Sheet

Rev. C | Page 22 of 68

ADC

The ADAU1977 contains four Δ-Σ ADC channels configured

as two stereo pairs with configurable differential/single-ended

inputs. The ADC can operate at a nominal sample rate of 32 kHz

up to 192 kHz. The ADCs include on-board digital antialiasing

filters with 79 dB stop-band attenuation and linear phase response.

Digital outputs are supplied through two serial data output pins

(one for each stereo pair) and a common frame clock (LRCLK)

and bit clock (BCLK). Alternatively, one of the TDM modes can

be used to support up to 16 channels on a single TDM data line.

With smaller amplitude input signals, a 10-bit programmable

digital gain compensation for an individual channel is provided

to scale up the output word to full scale. Care must be taken to

avoid overcompensation (large gain compensation), which leads

to clipping and THD degradation in the ADC.

The ADCs also have a dc-offset calibration algorithm to null

the systematic dc offset of the ADC. This feature is useful for dc

measurement applications.

Inductor Selection

For the boost converter to operate efficiently, the inductor selection

is critical. The two most important parameters for the inductor

are the saturation current rating and the dc resistance. The recom-

mended saturation rating for the inductor must be >1 A. The dc

resistance affects the efficiency of the boost converter. Assuming

that the board trace resistances are negligible for 80% efficiency,

the dc resistance of the inductor should be less than 50 mΩ.

Table 12 lists some of the recommended inductors for the

application.

Table 12. Recommended Inductors1

Value

Manufacturer

Manufacturer Part Number

2.2 μH

Würth Elektronik

7440430022

4.7 μH

Würth Elektronik

7440530047

1 Check with the manufacturer for the appropriate temperature ratings for a

given application.

The boost converter has a soft start feature that prevents inrush

current from the input source.

The boost converter has built-in overcurrent and overtemperature

protection. The input current to the boost converter is monitored

and if it exceeds the set current threshold for 1.2 ms, the boost

converter shuts down. The fault condition is recorded into

tion is cleared after reading the BOOST_OV bit (Bit 2) or the

BOOST_OC bit (Bit 0) in Register 0x02. The overcurrent

protection bit, OC_EN (Bit 1), or the overvoltage protection bit,

OV_EN (Bit 3), is on by default, and it is recommended not to

disable the bit.

Each protection circuit has two modes for recovery after a fault

event: autorecovery and manual recovery. The recovery mode

can be selected using Bit 0 of Register 0x03. The autorecovery

mode attempts to enable the boost converter after a set recovery

time, typically 20 ms. The manual recovery mode enables the boost

converter only if the user writes 1 to the MRCV bit (Bit 1). If the

fault persists, the boost converter remains in shutdown mode

until the fault is cleared.

The boost converter is capable of supplying the 42 mA of total

output current at the MICBIAS output. The boost converter has

overcurrent protection at the input; the threshold is around

900 mA peak. Ensure that the 3.3 V power supply feeding the

boost converter has built-in overcurrent protection because there is

no protection internal to ADAU1977 for a short circuit to any of

the ground pins (AGND/DGND/PGND) at the VBOOST_OUT

or VBOOST_IN pin.

By default, the boost converter is disabled on power-up to allow

the flexibility of connecting an external voltage source at the

VBOOST_IN pin to power the microphone bias circuit. The boost

converter can be enabled by using the BOOST_EN bit (Bit 2 of

ADC SUMMING MODES

The four ADCs can be grouped into either a single stereo ADC

or a single mono ADC to increase the signal-to-noise ratio (SNR)

for the application. Two options are available: one option for

summing two channels of the ADC and another option for

summing all four channels of the ADC. Summing is performed

in the digital block.

2-Channel Summing Mode

When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are

set to 01, the Channel 1 and Channel 2 ADC data are combined

and output from the SDATAOUT1 pin. Similarly, the Channel 3

and Channel 4 ADC data are combined and output from the

SDATAOUT2 pin. As a result, the SNR improves by 3 dB. For

this mode, both Channel 1 and Channel 2 must be connected to

the same input signal source. Similarly, Channel 3 and Channel 4

must be connected to the same input signal source.

4-Channel Summing Mode

When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are set

to 10, the Channel 1 through Channel 4 ADC data are combined

and output from the SDATAOUT1 pin. As a result, the SNR

improves by 6 dB. For this mode, all four channels must be

connected to the same input signal source.

ADAU1977WBCPZ-R7 Datasheet(PDF) 22 Page - Analog Devices

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