SSM4321 datasheet(14/24 Pages) AD

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SSM4321

Data Sheet

Rev. 0 | Page 14 of 24

THEORY OF OPERATION

OVERVIEW

The SSM4321 mono Class-D audio amplifier features a filterless

modulation scheme that greatly reduces the external component

count, conserving board space and, thus, reducing system cost.

The SSM4321 does not require an output filter but, instead, relies

on the inherent inductance of the speaker coil and the natural

filtering of the speaker and human ear to fully recover the audio

component of the square wave output.

Most Class-D amplifiers use some variation of pulse-width

modulation (PWM), but the SSM4321 uses Σ-Δ modulation to

determine the switching pattern of the output devices, resulting

in a number of important benefits.

•

Σ-Δ modulators do not produce a sharp peak with many

harmonics in the AM frequency band, as pulse-width

modulators often do.

•

Σ-Δ modulation reduces the amplitude of spectral compo-

nents at high frequencies, thus reducing EMI emissions that

might otherwise be radiated by speakers and long cable traces.

•

Due to the inherent spread-spectrum nature of Σ-Δ modu-

lation, the need for oscillator synchronization is eliminated

for designs that incorporate multiple SSM4321 amplifiers.

The SSM4321 also integrates overcurrent and overtemperature

protection.

POWER-DOWN OPERATION

The SSM4321 contains a clock loss detect circuit that works

with the BCLK input clock. When no BCLK is present, the part

automatically powers down all internal circuitry to its lowest

power state. When a BCLK is returned, the part automatically

powers up.

If BCLK is active but FSYNC or LRCLK is not present, the

amplifier continues to operate, but the ADC, sense blocks, and

digital processing are shut down, reducing quiescent current

when the output sense data is not needed. The ADC shutdown

feature is not available in PDM operating mode.

GAIN SELECTION

The gain of the SSM4321 can be set from 0 dB to 12 dB in 3 dB

steps using the GAIN pin and one (optional) external resistor.

The external resistor is used to select the 9 dB or 12 dB gain

setting (see Table 6).

Table 6. Setting the Gain of the SSM4321 with the GAIN Pin

Gain Setting (dB)

GAIN Pin Configuration

Tie to GND

Open

Tie to PVDD

Tie to GND through a 47 kΩ resistor

Tie to PVDD through a 47 kΩ resistor

POP-AND-CLICK SUPPRESSION

Voltage transients at the output of audio amplifiers can occur

when shutdown is activated or deactivated. Voltage transients

as low as 10 mV can be heard as an audible pop in the speaker.

Pops and clicks can also be classified as undesirable audible

transients generated by the amplifier system and, therefore, as

not coming from the system input signal.

The SSM4321 has a pop-and-click suppression architecture that

reduces these output transients, resulting in noiseless activation

and deactivation.

OUTPUT MODULATION DESCRIPTION

The SSM4321 uses three-level, Σ-Δ output modulation. Each

output can swing from GND to PVDD and vice versa. Ideally,

when no input signal is present, the output differential voltage is

0 V because there is no need to generate a pulse. In a real-world

situation, noise sources are always present.

Due to the constant presence of noise, a differential pulse is

generated, when required, in response to this stimulus. A small

amount of current flows into the inductive load when the differ-

ential pulse is generated.

Most of the time, however, the output differential voltage is 0 V,

due to the Analog Devices, Inc., three-level, Σ-Δ output modula-

tion. This feature ensures that the current flowing through the

inductive load is small.

When the user wants to send an input signal, an output pulse

(OUT+ and OUT−) is generated to follow the input voltage. The

differential pulse density (VOUT) is increased by raising the input

signal level. Figure 38 depicts three-level, Σ-Δ output modulation

with and without input stimulus.

OUTPUT > 0V

+5V

OUT+

+5V

OUT–

+5V

VOUT

OUTPUT < 0V

+5V

OUT+

+5V

OUT–

–5V

VOUT

OUTPUT = 0V

OUT+

+5V

OUT–

+5V

–5V

VOUT

Figure 38. Three-Level, Σ-Δ Output Modulation

With and Without Input Stimulus

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