SSM4321 datasheet(17/24 Pages) AD

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Data Sheet

SSM4321

Rev. 0 | Page 17 of 24

MULTICHIP I2S OPERATING MODE

A special multichip I2S mode is enabled when the part is wired

for TDM mode (BCLK and FSYNC not reversed) but the FSYNC

signal has a 50% duty cycle. If the FSYNC signal consists of one-

clock-cycle pulses, TDM operating mode is active instead.

The multichip I2S interface allows multiple chips to drive a single

I2S bus. Each chip takes control of the bus every two or four frames

(depending on the number of chips placed on the bus), allowing

a maximum of four chips on the bus. The SLOT pin assignments

determine the order of control. (See the Timing Diagrams,

Multichip I2S Mode section.)

Each frame also contains a 1-bit ID code, which is appended to

the current data in the frame. This code indicates the chip that

sent the data for that frame. Table 11 provides the mapping of

SLOT pin assignments to ID code.

Table 11. Multichip I2S Slot Selection

Chip No.

ID Code

SLOT Pin Configuration

0001

Tie to IOVDD

0010

Open

0100

Tie to GND

1000

Tie to IOVDD through a 47 kΩ resistor

The part is automatically configured for two-chip or four-chip

operation, depending on the number of chips detected on the bus.

The part starts up in four-chip operation, but after it detects that

Slot 3 and Slot 4 are unused, the part switches to two-chip oper-

ation. For two-chip operation, the first and second slots must be

used. If there are three chips on the bus, Slot 1 must be used along

with any two other slots.

Table 12 lists the FSYNC and BCLK rates that are supported in

multichip I2S mode.

Table 12. FSYNC and BCLK Rates in Multichip I2S Mode,

fS = 16 kHz to 48 kHz

Valid Slots

FSYNC Rate

BCLK Rate

1 and 2

2 × f

(32 kHz to 96 kHz)

128 × f

(2.048 MHz to 6.144 MHz)

1, 2, 3, 4

4 × f

(64 kHz to 128 kHz)

256 × f

(4.096 MHz to 12.288 MHz)

PDM OUTPUT MODE

By connecting the SLOT pin to GND through a 47 kΩ resistor,

the 1-bit PDM data from the ADCs can be output directly. In

PDM mode, a 1 MHz to 6.144 MHz clock must be provided on

Ball D3 (BCLK_TDM/PDM_CLK/LRCLK_I2S). PDM data is

sent on both edges of the clock and is output on Ball D1 (SDATAO/

PDM_DATA). (See the Timing Diagrams, PDM Mode section.)

In PDM mode, Ball D2 (FSYNC_TDM/BCLK_I2S) is used to

select the information that is output on the two possible channels

(see Table 13).

Table 13. FSYNC_TDM Pin Settings for PDM Mode

Output Data

FSYNC_TDM Pin

Current data on rising edge;

voltage data on falling edge

Tie to IOVDD

Current data on rising edge;

PVDD data on falling edge

Tie to GND

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