REV. 0

AD9804

–7–

VARIABLE GAIN AMPLIFIER (VGA) OPERATION

DETAILS

The VGA stage provides a gain range of 6 dB to 40 dB, pro-

grammable with 10-bit resolution through the serial digital

interface. The minimum gain of 6 dB is needed to match a 1 V

input signal with the ADC full-scale range of 2 V. When com-

pared to 1 V full-scale systems (such as ADI’s AD9803), the

equivalent gain range is 0 dB to 34 dB.

The VGA gain curve is divided into two separate regions. When

the VGA Gain Register code is between 0 and 511, the curve

follows a (1 + x)/(1 – x) shape, which is similar to a “linear-in-

dB” characteristic. From code 512 to code 1023, the curve follows

a “linear-in-dB” shape. The exact VGA gain can be calculated

for any Gain Register value by using the following two equations:

Code Range Gain Equation (dB)

0–511

512–1023

Gain = (0.0354)(code) + 3.6

As shown in the Analog Specifications, only the VGA gain range

from 2 dB to 36 dB has been specified. This corresponds to a

VGA gain code range of 95 to 1023.

VGA GAIN REGISTER CODE

40

0

127

255

383

511

639

767

895

1023

34

28

22

16

10

4

Figure 5. VGA Gain Curve

APPLICATIONS INFORMATION

The AD9804 is a complete Analog Front-End (AFE) product

for PC camera, digital still camera, and camcorder applications.

As shown in Figure 6, the CCD image (pixel) data is buffered

and sent to the AD9804 analog input through a series input

capacitor. The AD9804 performs the dc restoration, CDS, gain

adjustment, black level correction, and analog-to-digital con-

version. The AD9804’s digital output data is then processed by the

image processing ASIC. The internal registers of the AD9804

used to control gain, offset level, and other functions are pro-

grammed by the ASIC or microprocessor through a 3-wire serial

digital interface. A system timing generator provides the clock

signals for both the CCD and the AFE.

Generating the Reset (RSTB) Signal

After power-on, the AD9804 must be reset using Pin 43 (RSTB).

The reset pulse must be an active low signal, which goes low for

at least 100 ns after the power supplies have settled. After the

RSTB signal returns high, the AD9804 is internally reset to the

default VGA gain register value. If a system reset pulse is not

available, a simple RC network may be used, as shown in Figure

7. The time constant of this network should be comparable

to the power-on time of the AD9804’s power supplies. For

example, if the power supplies have a power-on time of 10 ms,

the RC network should have a time constant of 10 ms, giving

R = 10 k

Ω and C = 1.0 µF.

Serial writes to the AD9804 internal registers must not be per-

formed until 20

µs after the reset pulse has occurred. This allows

enough time for internal calibration routines to be completed.

SDATA and SCK may be active before the reset sequence, but

SL should be held logic HIGH until 20

µs or more after the reset.

Alternatively, placing series resistors close to the digital out-

put pins may help reduce noise.

Grounding and Decoupling Recommendations

As shown in Figure 7, a single ground plane is recommended for

the AD9804. This ground plane should be as continuous as

possible, particularly around Pins 25 through 39. This will ensure

that all analog decoupling capacitors provide the lowest possible

impedance path between the power and bypass pins and their

respective ground pins. All decoupling capacitors should be

located as close as possible to the package pins. A single clean

power supply is recommended for the AD9804, but a separate

digital driver supply may be used for DRVDD (Pin 13). DRVDD

should always be decoupled to DRVSS (Pin 14), which should

be connected to the analog ground plane. Advantages of using a

separate digital driver supply include using a lower voltage (2.7 V)

to match levels with a 2.7 V ASIC, reducing digital power dissipa-

tion, and reducing potential noise coupling. If the digital outputs

(Pins 3–12) must drive a load larger than 20 pF, buffering is

recommended to reduce digital code transition noise.

CCD

CCDIN

BUFFER

0.1 F

VGA GAIN

SERIAL

INTERFACE

DIGITAL

OUTPUTS

DIGITAL IMAGE

PROCESSING

ASIC

TIMING

GENERATOR

V-DRIVE

CCD

TIMING

CDS/CLAMP

TIMING

AD9804

Figure 6. System Block Diagram