Broadcom Confidential

- 12 -

ACPL-P302/ACPL-W302

Data Sheet

A high CMR LED drive circuit must keep the LED on during

common mode transients. This is achieved by overdriving the

LED current beyond the input threshold so that it is not pulled

below the threshold during a transient. A minimum LED

current of 7 mA provides adequate margin over the maximum

LED Drive Circuit Considerations for Ultra High

CMR Performance

Without a detector shield, the dominant cause of optocoupler

CMR failure is capacitive coupling from the input side of the

optocoupler, through the package, to the detector IC as shown

in Figure 19. The ACPL-P302/W302 improves CMR performance

by using a detector IC with an optically transparent Faraday

shield, which diverts the capacitively coupled current away

from the sensitive IC circuitry. However, this shield does not

eliminate the capacitive coupling between the LED and opto-

coupler pins 5-8 as shown in Figure 20. This capacitive cou-

pling causes perturbations in the LED current during common

mode transients and becomes the major source of CMR

failures for a shielded optocoupler. The main design objective

of a high CMR LED drive circuit becomes keeping the LED in

the proper state (on or off) during common mode transients.

For example, the recommended application circuit (Figure

17), can achieve 10 kV/µs CMR while minimizing component

complexity.

Techniques to keep the LED in the proper state are discussed

in the next two sections.

Figure 21 Equivalent Circuit for Figure 15 During CM Transient

The open collector drive circuit, shown in Figure 22, can not

and it is not recommended for applications requiring ultra

the recommended application circuit (Figure 17), does achieve

ultra high CMR performance by shunting the LED in the off

state.

Figure 19 Optocoupler Input to Output Capacitance Model for

Unshielded Optocouplers

Figure 20 Optocoupler Input to Output Capacitance Model for

Shielded Optocouplers

Figure 22 Not Recommended Open Collector Drive Circuit

long as the low state voltage developed across the logic gate is

failure will occur.

Figure 23 Recommended LED Drive Circuit for Ultra-High CMR

Dead Time and Propagation Delay Specifications

C

LEDP

C

LEDN

6

1

5

2

4

3

C

LEDP

C

LEDN

6

1

5

2

4

3

C

LEDP

C

LEDN

6

1

5

2

4

3

SHIELD

C

LED01

C

LED02

C

LEDP

C

LEDN

6

1

5

2

4

3

SHIELD

C

LED01

C

LED02

C

LEDP

C

LEDN

6

1

5

2

4

3

SHIELD

I

LEDP

R

g

V

+

-

0.1 mF

THEARROWS INDICATETHEDIRECTION

OFCURRENTFLOW DURING - dV

+5 V

V

SAT

+

-

V

CM

I

+

-

V

SAT

+

-

V

SAT

+

-

·

·

C

LEDP

C

LEDN

6

1

5

2

4

3

SHIELD

I

LEDN

+5 V

Q1

C

LEDP

C

LEDN

6

1

5

2

4

3

SHIELD

I

LEDN

+5 V

Q1

Q1

C

LEDP

C

LEDN

6

1

5

2

4

3

SHIELD

+5 V

C

LEDP

C

LEDN

6

1

5

2

4

3

+5 V