LTC2230 datasheet(22/28 Pages) LINER

22 / 28 page

LTC2230/LTC2231

22301p

Digital Output Buffers (LVDS Mode)

Figure 13b shows an equivalent circuit for a differential

output pair in the LVDS output mode. A 3.5mA current is

steered from OUT+ to OUT– or vice versa which creates a

±350mV differential voltage across the 100Ω termination

resistor at the LVDS receiver. A feedback loop regulates

the common mode output voltage to 1.25V. For proper

operation each LVDS output pair needs an external 100Ω

termination resistor, even if the signal is not used (such as

OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the

PC board traces for each LVDS output pair should be

routed close together. To minimize clock skew all LVDS PC

board traces should have about the same length.

APPLICATIO S I FOR ATIO

Overflow Bit

An overflow output bit indicates when the converter is

overranged or underranged. In CMOS mode, a logic high

on the OFA pin indicates an overflow or underflow on the

A data bus, while a logic high on the OFB pin indicates an

overflow or underflow on the B data bus. In LVDS mode,

a differential logic high on the OF+/OF– pins indicates an

overflow or underflow.

Output Clock

The ADC has a delayed version of the ENC+ input available

as a digital output, CLKOUT. The CLKOUT pin can be used

to synchronize the converter data to the digital system. This

is necessary when using a sinusoidal encode. In all CMOS

modes, A bus data will be updated just after CLKOUTA rises

and can be latched on the falling edge of CLKOUTA. In demux

CMOS mode with interleaved update, B bus data will be

updated just after CLKOUTB rises and can be latched on the

falling edge of CLKOUTB. In demux CMOS mode with si-

multaneous update, B bus data will be updated just after

CLKOUTB falls and can be latched on the rising edge of

CLKOUTB. In LVDS mode, data will be updated just after

CLKOUT+/CLKOUT– rises and can be latched on the falling

edge of CLKOUT+/CLKOUT–.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven. For

example if the converter is driving a DSP powered by a 1.8V

supply then OVDD should be tied to that same 1.8V supply.

In the CMOS output mode, OVDD can be powered with any

voltage up to the VDD ofthepart.OGNDcanbepoweredwith

any voltage from GND up to 1V and must be less than OVDD.

The logic outputs will swing between OGND and OVDD.

In the LVDS output mode, OVDD should be connected to a

3.3V supply and OGND should be connected to GND.

Output Enable

The outputs may be disabled with the output enable pin, OE.

In CMOS or LVDS output modes OE high disables all data

outputs including OF and CLKOUT. The data access and bus

LTC2230/LTC2231

22301 F13b

OVDD

LVDS

RECEIVER

OGND

1.25V

OUT+

OUT–

100Ω

–

3.5mA

10k

Figure 13b. Digital Output in LVDS Mode

Table 2. MODE Pin Function

Clock Duty

MODE Pin

Output Format

Cycle Stablizer

Straight Binary

Off

1/3VDD

Straight Binary

2/3VDD

2’s Complement

VDD

2’s Complement

Off

Data Format

The LTC2230/LTC2231 parallel digital output can be se-

lected for offset binary or 2’s complement format. The

format is selected with the MODE pin. Connecting MODE

to GND or 1/3VDD selects straight binary output format.

Connecting MODE to 2/3VDD or VDD selects 2’s comple-

ment output format. An external resistor divider can be

used to set the 1/3VDD or 2/3VDD logic values. Table 2

shows the logic states for the MODE pin.

LTC2230 Datasheet(PDF) 22 Page - Linear Technology

LTC2230 Datasheet(HTML) 22 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL