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ICS2309 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS2309 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 9 page  ICS2309 MDS 2309 D 1 Revision 052405 Integrat ed Circuit Syst ems ● 52 5 Ra ce Street, San Jose, CA 9 512 6 ● tel (408 ) 297 -120 1 ● www.icst.com 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Description The ICS2309 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on ICS’ proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides eight low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The ICS2309 is available in two different versions. The ICS2309-1 is the base part. The ICS2309-1H is a high drive version with faster rise and fall times. Features • Clock outputs from 10 to 133 MHz • Zero input-output delay • Eight low skew (<250 ps) outputs • Device-to-device skew <700 ps • Full CMOS outputs with 25 mA output drive capability at TTL levels • 5 V tolerant CLKIN • Tri-state mode for board-level testing • Advanced, low power, sub-micron CMOS process • Operating voltage of 3.3 V • Industrial temperature range available • Packaged in 16-pin SOIC and TSSOP (-1H version only) • Pb (lead) free package available for -1H version (16-pin TSSOP only) Block Diagram CLKA4 CLKB1 CLKA3 CLKB2 CLKB3 CLKA2 CLKA1 CLKB4 CLKIN Control Logic 1 0 S2, S1 2 PLL VDD 2 GND 2 CLKOUT |
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