16

Third party brands and names are the property of their respective owners.

Integrated

Circuit

Systems, Inc.

ICS950901

Fig. 1

Shared Pin Operation -

Input/Output Pins

The I/O pins designated by (input/output) serve as dual

signal functions to the device. During initial power-up, they

act as input pins. The logic level (voltage) that is present on

these pins at this time is read and stored into a 5-bit internal

data latch. At the end of Power-On reset, (see AC

characteristics for timing values), the device changes the

mode of operations for these pins to an output function. In

this mode the pins produce the specified buffered clocks to

external loads.

To program (load) the internal configuration register for

these pins, a resistor is connected to either the VDD (logic 1)

power supply or the GND (logic 0) voltage potential. A 10

Kilohm (10K) resistor is used to provide both the solid CMOS

programming voltage needed during the power-up

programming period and to provide an insignificant load on

the output clock during the subsequent operating period.

Figure 1 shows a means of implementing this function when

Via to

VDD

Clock trace to load

Series Term. Res.

Programming

Header

Via to Gnd

Device

Pad

2K

W

8.2K

W

a switch or 2 pin header is used. With no jumper is installed

the pin will be pulled high. With the jumper in place the pin

will be pulled low. If programmability is not necessary, than

only a single resistor is necessary. The programming

resistors should be located close to the series termination

resistor to minimize the current loop area. It is more important

to locate the series termination resistor close to the driver

than the programming resistor.