ICS950901 datasheet(1/20 Pages) ICST

Part #	ICS950901

Description	Programmable Timing Control Hub for P4

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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1 / 20 page

Integrated

Circuit

Systems, Inc.

ICS950901

Block Diagram

0474F—05/25/05

Pin Configuration

Recommended Application:

VIA P4X266 chipset with PC133 or DDR memory.

Output Features:

•

2 - Pair of differential CPU clocks @ 3.3V

•

1 - Pair of differential push pull CPU_CS clocks @ 2.5V

•

3 - AGP @ 3.3V

•

9 - PCI @ 3.3V

•

2 - IOAPIC @ 2.5V

•

1 - 48MHz @ 3.3V fixed

•

1 - 24_48MHz @ 3.3V

•

1 - REF @ 3.3V, 14.318MHz

Features/Benefits:

•

Programmable output frequency.

•

Programmable output divider ratios.

•

Programmable output rise/fall time.

•

Programmable output skew.

•

Programmable spread percentage for EMI control.

•

Watchdog timer technology to reset system

if system malfunctions.

•

Programmable watch dog safe frequency.

•

Support I

2C Index read/write and block read/write

operations.

•

For DDR and or PC133 SDRAM system use ICS93718

as the memory buffer.

•

Uses external 14.318MHz crystal.

Key Specifications:

•

CPU_CS - CPU0: <±250ps

•

CPU_CS - AGP: <±250ps

•

PCI - PCI: <500ps

•

CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns

Programmable Timing Control Hub™ for P4™

1. These outputs have 2X drive strength.

* These inputs have a internal Pull-up resistor

of 120K to VDD

** These inputs have a internal pull-down to GND

48-Pin 300-mil SSOP

Frequency Table

I REF

PLL2

PLL1

Spread

Spectr

Spectrum

um

48MHz

24_48MHz

IO

IOAPIC (1:0)

APIC (1:0)

PCICLK (7:0)

A

AGPCLK (2:0)

GPCLK (2:0)

RESET#

PCICLK_F

3

X1

X2

XT

XTAL

AL

OSC

CPU

DIVDER

CPU

DIVDER

IO

IOAPIC

APIC

DIVDER

PCI

DIVDER

A

AGP

GP

DIVDER

Stop

SEL24_48

SD

SDA

AT

TA

A

SCLK

FS (3:0)

PD#

PCI_ST

PCI_STOP#

OP#

CPU_ST

CPU_STOP#

OP#

MUL

MULTI_SEL

TI_SEL

Vtt_PWRGD#

Control

Logic

Config.

Reg.

/ 2

REF

CPUCLKT_(1:0)

CPUCLKC_(1:0)

CPUCLKT_CS

CPUCLKC_CS

3

S

F2

S

F1

S

F0

S

F

K

L

C

U

P

C

z

H

M

P

G

A

z

H

M

K

L

C

I

C

P

z

H

M

00

0

7

6

.

6

66

6

.

6

63

3

.

3

00

0

1

0

.

0

17

6

.

6

63

3

.

3

001

0

3

.

3

17

6

.

6

63

3

.

3

001

1

0

.

0

26

6

.

6

63

3

.

3

01

0

9

.

0

17

2

.

7

63

6

.

3

01

0

1

0

.

3

0

17

6

.

8

63

3

.

4

3

01

1

0

.

7

0

13

3

.

1

77

6

.

5

3

01

1

0

.

0

1

13

3

.

3

77

6

.

6

3

100

0

9

.

3

15

9

.

6

68

4

.

3

100

1

3

.

7

3

16

6

.

8

63

3

.

4

3

10

1

0

.

0

4

10

0

.

0

70

0

.

5

3

10

1

6

.

2

4

13

3

.

1

77

6

.

5

3

11

0

3

.

5

4

16

6

.

2

73

3

.

6

3

11

0

1

6

.

6

4

13

3

.

3

77

6

.

6

3

11

1

0

3

.

3

5

16

6

.

6

73

3

.

8

3

11

1

0

.

0

6

10

0

.

0

80

0

.

0

4

1

*SEL24_48/REF

VDDREF

GND

X1

X2

VDD48

**FS3/48MHz

**FS2/24_48MHz

GND

*FS0/PCICLK_F

**FS1/PCICLK0

PCICLK1

GND

PCICLK2

PCICLK3

VDDPCI

PCICLK4

PCICLK5

PCICLK6

GND

PCICLK7

*PD#

AGPCLK0

VDDAGP

VDDAPIC (2.5V)

GND

IOAPIC0

IOAPIC1

GND

VDDCPU_CS (2.5V)

CPUCLKT_CS

CPUCLKC_CS

CPUCLKT_0

CPUCLKC_0

VDDCPU (3.3V)

I REF

GND

CPUCLKT_1

CPUCLKC_1

Vtt_PWRGD#

CPU_STOP#*

PCI_STOP#*

RESET#

SDATA

SCLK

AGPCLK2

AGPCLK1

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

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