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INA821 Datasheet(PDF) 25 Page - Texas Instruments |
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INA821 Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 36 page ![]() + ± + ± + ± 10 k 24.7 k 10 k 10 k 10 k 24.7 k Over- Voltage Protection Over- Voltage Protection RG REF +VS V- OUT V+ -VS -IN +IN RG RREF RG 25 INA821 www.ti.com SBOS893 – AUGUST 2018 Product Folder Links: INA821 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Reference Pin The output voltage of the INA821 is developed with respect to the voltage on the reference pin (REF.) Often in dual-supply operation, the reference pin (pin 6) connects to the low-impedance system ground. In single-supply operation, offsetting the output signal to a precise midsupply level is useful (for example, 2.5 V in a 5-V supply environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the output so that the INA821 drives a single-supply ADC. The voltage source applied to the reference pin must have a low output impedance. As shown in Figure 61, any resistance at the reference pin ( RREF in Figure 61) is in series with one of the internal 40-kΩ resistors. Figure 61. Parasitic Resistance Shown at the Reference Pin The parasitic resistance at the reference pin (RREF) creates an imbalance in the four resistors of the internal difference amplifier, resulting in degraded common-mode rejection ratio (CMRR). Figure 62 shows the degradation in CMRR of the INA821 for increasing resistance at the reference pin. For the best performance, keep the source impedance to the REF pin (RREF) below 5 Ω. |
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