ADV7480

Data Sheet

TIMING SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 3.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

CLOCK AND CRYSTAL

Nominal Frequency1

28.63636

MHz

Frequency Stability1

±50

ppm

Input LLC Clock Frequency Range2,3

DVDDIO = 3.14 V to 3.46 V

13.5

148.5

MHz

Output LLC Clock Frequency Range2,3

DVDDIO = 3.14 V to 3.46 V

13.5

148.5

MHz

SPI_SCLK Frequency3

10

MHz

I2S_SCLK Frequency3

12.288

MHz

I2S_MCLK Frequency3

24.576

MHz

SCLK Frequency

400

kHz

SCLK Minimum Pulse Width High

0.6

µs

SCLK Minimum Pulse Width Low

1.3

µs

Hold Time (Start Condition)

0.6

µs

Setup Time (Start Condition)

0.6

µs

SDATA Setup Time

100

ns

SCLK and SDATA Rise Times

300

ns

SCLK and SDATA Fall Times

300

ns

Setup Time (Stop Condition)

0.6

µs

SPI PORT

Slave Mode

SPI_CS Falling Edge to SPI_SCLK

Active Edge

SPI_SCLK active edge (rising or falling

edge) depends on the values of CPHA

and CPOL

35

ns

SPI_SCLK Active Edge to SPI_CS

Rising Edge

SPI_SCLK active edge (rising or falling

edge) depends on the values of CPHA

and CPOL

35

ns

SPI_CS Pulse Width

50

ns

SPI_SCLK High Time3

45

55

% duty

cycle

SPI_SCLK Low Time3

45

55

% duty

cycle

SPI_MOSI Setup Time

SPI Mode 0, SPI Mode 3

0

ns

SPI_MOSI Hold Time

SPI Mode 0, SPI Mode 3

35

ns

SPI_SCLK Falling Edge to SPI_MISO

Start of Data Invalid3

SPI Mode 0, SPI Mode 3

50

ns

SPI_SCLK Falling Edge to SPI_MISO

End of Data Invalid3

SPI Mode 0, SPI Mode 3

50

ns

SPI_MOSI Setup Time

SPI Mode 1, SPI Mode 2

0

ns

SPI_MOSI Hold Time

SPI Mode 1, SPI Mode 2

35

ns

SPI_SCLK Rising Edge to SPI_MISO

Start of Data Invalid

SPI Mode 1, SPI Mode 2

35

ns

SPI_SCLK Rising Edge to SPI_MISO

End of Data Invalid

SPI Mode 1, SPI Mode 2

35

ns

RESET FEATURE

RESET Pulse Width1

5

ms

Rev. 0 | Page 8 of 19