Data Sheet

ADV7480

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

DVDDIO = 3.14 V to 3.46 V

45

55

% duty

cycle

45

55

% duty

cycle

SDR and DDR Modes Setup Time

Data latched on rising edge

1

ns

SDR and DDR Modes Hold Time

Data latched on rising edge

1

ns

DDR Mode Setup Time

Data latched on falling edge

1

ns

DDR Mode Hold Time

Data latched on falling edge

1

ns

DVDDIO = 3.14 V to 3.46 V

LLC High Time

40

60

% duty

cycle

LLC Low Time

40

60

% duty

cycle

At P0 to P7 output pin, data latched

on rising edge

1.98

ns

At P0 to P7 output pin, data latched

on rising edge

2.50

ns

At P0 to P7 output pin, data latched

on rising edge

1.66

ns

At P0 to P7 output pin, data latched

on rising edge

3.52

ns

At P0 to P7 output pin, data latched

on falling edge

1.71

ns

At P0 to P7 output pin, data latched

on falling edge

3.17

ns

I2S_SCLK High Time

45

55

% duty

cycle

I2S_SCLK Low Time

45

55

% duty

cycle

I2S_LRCLK Data Transition Time

End of valid data to I2S_SCLK falling

edge

10

ns

I2S_SCLK falling edge to start of valid

data

10

ns

I2S_SDATA Data Transition Time

End of valid data to I2S_SCLK falling

edge

5

ns

I2S_SCLK falling edge to start of valid

data

5

ns

1

Required by design.

2

The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.

3

Guaranteed by design.

4

These specifications only apply when the LLC_DLL_PHASE[4:0] (IO Map, Register 0x0C[4:0]) is set to 00000

5

Guaranteed by lab characterization.

Rev. 0 | Page 9 of 19