ADV7604 datasheet(6/20 Pages) AD

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ADV7604

Data Sheet

Rev. D | Page 6 of 20

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

I2C PORTS

Normal Mode

xCL Frequency2

100

kHz

xCL Minimum Pulse Width High2

4.0

μs

xCL Minimum Pulse Width

Low2

4.7

μs

Hold Time (Start Condition)2

4.0

μs

Setup Time (Start Condition)2

4.7

μs

xDA Setup Time2

250

xCL and xDA Rise Time2

1000

xCL and xDA Fall Time2

300

Setup Time (Stop Condition)

4.0

μs

DATA AND CONTROL OUTPUTS3

Data Output Transition Time SDR

(CP)

t11

End of valid data to negative clock edge

0.55

Data Output Transition Time SDR

(CP)

t12

Negative clock edge to start of valid data

1.0

VIDEO I2S PORT

Master Mode

SCLK Mark Space Ratio

t13:t14

45:55

55:4

% duty

cycle

LRCLK Data Transition Time

t15

End of valid data to negative SCLK

edge

LRCLK Data Transition Time

t16

Negative SCLK edge to start of valid

data

I2Sx Data Transition Time4

t17

End of valid data to negative SCLK

edge

I2Sx Data Transition Time4

t18

Negative SCLK edge to start of valid

data

1 The XTAL_CTRL bit in AFE Map 0x4C[7:6] = 10b. This configures the XTAL pins for external oscillator operation. A 1.8 V oscillator must be used.

2 The prefix x refers to S, DDCA_S, DDCB_S, DDCC_S, and DDCD_S.

3 LLC DLL disabled.

4 The suffix x refers to 0, 1, 2, and 3.

TIMING DIAGRAMS

xDA

xCL

NOTES

1. x REFERS TO S, DDCA_S, DDCB_S, DDCC_S, DDCD_S.

Figure 2. I2C Timing

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