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FSSD06 Datasheet(PDF) 3 Page - ON Semiconductor |
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FSSD06 Datasheet(HTML) 3 Page - ON Semiconductor |
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3 / 15 page  © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSSD06 • Rev. 1.0.5 2 Pin Configuration 12 11 6 7 8 9 10 15 17 18 19 VDDH GND 1 224 23 13 14 3 4 5 20 21 22 DAT[2] 1CLK DAT[3] CLK DAT[0] CMD DAT[1] 2CMD VDDC2 1DAT[1] 2DAT[2] VDDC1 1DAT[0] 2DAT[3] 16 DAT[3] CMD VDDH GND CLK 1CLK 2CMD DAT[0] 1DAT[0] 1DAT[1] 2DAT[3] 2DAT[2] 1 2 3 4 5 6 24 10 9 8 7 14 13 12 11 19 18 17 16 15 23 22 21 20 Figure 2. MLP Pin Assignments Figure 3. UMLP Pin Assignments Pin Definitions Name Description VDDH Power Supply (Host ASIC) VDDC1, VDDC2 Power Supply (SDIO Peripheral Card Ports) /OE Output Enable (Active Low) S Select Pin 1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD SDIO Card Ports DAT[3:0], CMD SDIO Common Ports CLK, 1CLK, 2CLK Clock Path Ports Truth Table /OE S Function LOW LOW CMD, CLK, DAT[3:0] connected to 1CMD, 1CLK, 1DAT[3:0]; 2CLK pulled HIGH via RPU LOW HIGH CMD, CLK, DAT[3:0] connected to 2CMD, 2CLK, 2DAT[3:0]; 1CLK pulled HIGH via RPU HIGH X All Ports High Impedance; 1CLK, 2CLK pulled HIGH via RPU |
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