WM8988 datasheet(39/58 Pages) CIRRUS

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WM8988

Rev 4.2

AUDIO INTERFACE OUTPUT TRISTATE

DACLRC and BCLK to inputs. In Slave mode (MASTER=0) LRC and BCLK are by default configured

as inputs and only ADCDAT will be tri-stated, (see Table 32).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24(18h)

Additional

Control (2)

TRI

Tristates ADCDAT and switches ADCLRC,

DACLRC and BCLK to inputs.

0 = ADCDAT is an output, LRC and BCLK are

inputs (slave mode) or outputs (master mode)

1 = ADCDAT is tristated, LRC and BCLK are

inputs

Table 32 Tri-stating the Audio Interface

MASTER MODE LRC ENABLE

In Master mode the lrclk (LRC) is enabled by default only when the DAC is enabled. If ADC only

operation in Master mode is required register bit LRCM must be set in order to generate an lrclk. For

DAC only operation LRCM may be set to ‘0’.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24(18h)

Additional

Control (2)

LRCM

Selects disable mode for LRC

0 = LRC disabled when DAC (Left and Right)

disabled.

1 = LRC disabled only when ADC (Left and

Right) and DAC (Left and Right) are disabled.

Table 33 LRC Enable

BIT CLOCK MODE

The default master mode bit clock generator produces a bit clock frequency based on the sample rate

and input MCLK frequency as shown in Table 36. When enabled by setting the appropriate BCM[1:0]

bits, the bit clock mode (BCM) function overrides the default master mode bit clock generator to

produce the bit clock frequency shown in the table below:

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

Clocking and

Sample Rate

Control

8:7

BCM[1:0]

BCLK Frequency

00 = BCM function disabled

01 = MCLK/4

10 = MCLK/8

11 = MCLK/16

Table 34 Master Mode BCLK Frequency Control

The BCM mode bit clock generator produces 16 or 24-bit clock cycles per sample. The number of bit

clock cycles per sample in this mode is determined by the word length bits (WL[1:0]) in the Digital

Audio Interface Format register (R7). When these bits are set to 00, there will be 16-bit clock cycles

per sample. When these bits are set to 01, 10 or 11, there will be 24 bit clock cycles per sample.

Please refer to Figure 18.

In order to use BCM either the ADC must be enabled or, if the ADC is disabled, the LRCM bit must be

set and the DAC enabled. When the BCM function is enabled, the following restrictions apply:

1. The bit clock invert (BCLKINV) function is not available.

2. DSP late digital audio interface mode is not available and must not be enabled.

WM8988 Datasheet(PDF) 39 Page - Cirrus Logic

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