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AD9510 Datasheet(PDF) 45 Page - Analog Devices |
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AD9510 Datasheet(HTML) 45 Page - Analog Devices |
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45 / 56 page  Data Sheet AD9510 Rev. C | Page 45 of 56 Addr (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Def. Value (Hex) Notes 3E LVPECL OUT2 Not used Output level[3:2] Power-down[1:0] 08 On 3F LVPECL OUT3 Not used Output level[3:2] Power-down[1:0] 08 On 40 LVDS_CMOS OUT4 Not used CMOS inverted driver on Logic select Output level[2:1] Output power 02 LVDS, on 41 LVDS_CMOS OUT5 Not used CMOS inverted driver on Logic select Output level[2:1] Output power 02 LVDS, on 42 LVDS_CMOS OUT6 Not used CMOS inverted driver on Logic select Output level[2:1] Output power 03 LVDS, off 43 LVDS_CMOS OUT7 Not used CMOS inverted driver on Logic select Output level[2:1] Output power 03 LVDS, off 44 Not used CLK1 and CLK2 Input receivers 45 Clocks select, power-down (PD) options Not used CLKs in PD REFIN PD CLK to PLL PD CLK2 PD CLK1 PD Select CLK IN 01 All clocks on, select CLK1 46, 47 Not used Dividers 48 Divider 0 Low cycles[7:4] High cycles[3:0] 00 Divide by 2 49 Divider 0 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0 4A Divider 1 Low cycles[7:4] High cycles[3:0] 00 Divide by 2 4B Divider 1 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0 4C Divider 2 Low cycles[7:4] High cycles[3:0] 11 Divide by 4 4D Divider 2 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0 4E Divider 3 Low cycles[7:4] High cycles[3:0] 33 Divide by 8 4F Divider 3 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0 50 Divider 4 Low cycles[7:4] High cycles[3:0] 00 Divide by 2 51 Divider 4 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0 52 Divider 5 Low cycles[7:4] High cycles[3:0] 11 Divide by 4 53 Divider 5 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0 54 Divider 6 Low cycles[7:4] High cycles[3:0] 00 Divide by 2 55 Divider 6 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0 56 Divider 7 Low cycles[7:4] High cycles[3:0] 00 Divide by 2 57 Divider 7 Bypass No sync Force Start H/L Phase offset[3:0] 00 Phase = 0 Function 58 FUNCTION Pin and sync Not used Set FUNCTION Pin PD sync PD all ref. Sync reg. Sync select Sync enable 00 FUNCTION pin = RESETB 59 Not used 5A Update registers Not used Update registers 00 Self- clearing bit END |
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