DS2282

022798 11/22

NAME

DESCRIPTION

CLEARABLE

R/W

UASICR

29

R

No

UAS Interval Count Registers. A set of 96 16–bit registers

that contain the Unavailable Second counts for the previous

96 individual 15–minute periods. Most recent interval is read

first.

BESICR

2A

R

No

BES Interval Count Registers. A set of 96 16–bit registers

that contain the Bursty Errored Second counts for the pre-

vious 96 individual 15–minute periods. Most recent interval

is read first.

SESICR

2B

R

No

SES Interval Count Registers. A set of 96 16–bit registers

that contain the Severely Errored Second counts for the pre-

vious 96 individual 15–minute periods. Most recent interval

is read first.

CSLFICR

2C

R

No

CSS & LOFC Interval Count Registers. A set of 96 16–bit

registers that contain the Controlled Slip and Loss Of Frame

counts for the previous 96 individual 15–minute periods. The

8–bit CSS count is the LSB and the 8–bit LOFC count is in

the MSB. Most recent interval is read first.

ESDCR

2D

R

No

ES Day Count Registers. A 16–bit register that counts the

number of Errored Seconds in the previous 24–hour period.

UEEER

36

R

Yes

User ESF Error Event Register. 16–bit register that mimics

the ESFEER for user access.

UASDCR

2E

R

No

UAS Day Count Registers. A 16–bit register that counts

the number of Unavailable Seconds in the previous 24–hour

period.

BESDCR

2F

R

No

BES Day Count Registers. A 16–bit register that counts

the number of Bursty Errored Seconds in the previous

24–hour period.

SESDCR

30

R

No

SES Day Count Registers. A 16–bit register that counts the

number of Severely Errored Seconds in the previous

24–hour period.

CSLFDCR

31

R

No

CSS & LOFC Day Count Registers. A 16–bit register that

counts the number of Controlled Slip Seconds and Loss Of

Frames in the previous 24–hour period. The 8–bit CSS

count is in the LSB and the 8–bit LOFC count is in the MSB.

VITR

32

R

No

Valid Interval Total Register. An 8–bit register that indi-

cates the number of valid 15–minute intervals in the previous

24–hour period.

RMSR

33

R

Yes

Request Message Status Register. An 8–bit register that

indicates which (if any) request message is being received.

CR

34

W

No

Control Register. An 8–bit register that selects which ad-

dress the DS2282 will respond to.

NOTES:

1. All of the registers in the DS2282 that count events will saturate at their maximum possible count; they do not

roll over. For example, all the 16–bit registers stop at a count of 65,535. They do not roll over to zero and

continue counting.

2. Values indicated in hexadecimal format.

3. All register read/written LSB first.