AD9115BCPZ datasheet(44/52 Pages) AD

44 / 52 page

AD9114/AD9115/AD9116/AD9117

Data Sheet

Rev. D | Page 44 of 52

where:

IIREF

= VREFIO/IRSET

(4)

IQREF = VREFIO/QRSET

IIOUTFS

= 32 × VREFIO/IRSET

(5)

IQOUTFS

= 32 × VREFIO/QRSET

A differential pair (IOUTP/IOUTN or QOUTP/QOUTN)

typically drives a resistive load directly or via a transformer. If

dc coupling is required, the differential pair (IOUTP/IOUTN or

QOUTP/QOUTN) should be connected to matching resistive

loads, xRLOAD, that are tied to analog common, AVSS. The single-

ended voltage output appearing at the positive and negative nodes is

VIOUTP

= IOUTP × IRLOAD

(6)

VQOUTP

= QOUTP × QRLOAD

VIOUTN

= IOUTN × IRLOAD

(7)

VQOUTN

= QOUTN × QRLOAD

To achieve the maximum output compliance of 1 V at the nominal

20 mA output current, IRLOAD = QRLOAD must be set to 50 Ω.

Substituting the values of IOUTP, IOUTN, IxREF, and VIDIFF can

be expressed as

VIDIFF

= {(2 × IDAC CODE − (2N − 1))/2N} ×

(32 × VREFIO/IRSET) × IRLOAD

(8)

Equation 8 highlights some of the advantages of operating the

AD9114/AD9115/AD9116/AD9117 differentially. First, the

differential operation helps cancel common-mode error sources

associated with IOUTP and IOUTN, such as noise, distortion,

and dc offsets. Second, the differential code-dependent current and

subsequent voltage, VIDIFF, is twice the value of the single-ended

voltage output (that is, VIOUTP or VIOUTB), thus providing twice the

signal power to the load. Note that the gain drift temperature

performance for a single-ended output (VIOUTP and VIOUTN) or

differential output of the AD9114/AD9115/AD9116/ AD9117

can be enhanced by selecting temperature tracking resistors for

xRLOAD and xRSET because of their ratiometric relationship, as

shown in Equation 8.

ANALOG OUTPUT

The complementary current outputs in each DAC, IOUTP/

IOUTN and QOUTP/QOUTN, can be configured for single-

ended or differential operation. IOUTP/IOUTN and QOUTP/

QOUTN can be converted into complementary single-ended

voltage outputs, VIOUTP and VIOUTN as well as VQOUTP and VQOUTN via

a load resistor, xRLOAD, as described in the DAC Transfer Function

section by Equation 6 through Equation 8. The differential

voltages, VIDIFF and VQDIFF, existing between VIOUTP and VIOUTN,

and VQOUTP and VQOUTN, can also be converted to a single-ended

voltage via a transformer or a differential amplifier configuration.

The ac performance of the AD9114/AD9115/AD9116/AD9117 is

optimum and is specified using a differential transformer-coupled

output in which the voltage swing at IOUTP and IOUTN is

limited to ±0.5 V. The distortion and noise performance of the

AD9114/AD9115/AD9116/AD9117 can be enhanced when it is

configured for differential operation. The common-mode error

sources of both IOUTP/IOUTN and QOUTP/QOUTN can be

significantly reduced by the common-mode rejection of a

transformer or differential amplifier. These common-mode error

sources include even-order distortion products and noise.

The enhancement in distortion performance becomes more

significant as the frequency content of the reconstructed waveform

increases and/or its amplitude increases. This is due to the first-

order cancellation of various dynamic common-mode distortion

mechanisms, digital feedthrough, and noise. Performing a

differential-to-single-ended conversion via a transformer also

provides the ability to deliver twice the reconstructed signal

power to the load (assuming no source termination). Because

the output currents of IOUTP/IOUTN and QOUTP/QOUTN

are complementary, they become additive when processed

differentially.

SELF-CALIBRATION

The AD9114/AD9115/AD9116/AD9117 have a self-calibration

feature that improves the DNL of the device. Performing a self-

calibration on the device improves device performance in low

frequency applications. The device performance in applications

where the analog output frequencies are above 5 MHz are generally

influenced more by dynamic device behavior than by DNL and,

in these cases, self-calibration is unlikely to produce measurable

benefits. The calibration clock frequency is equal to the DAC clock

divided by the division factor chosen by the DIVSEL value. There

is a fixed pre-divider of 16 and it is multiplied by the DIVSEL,

which has a range of divide by 2 -256. Each calibration clock

cycle is between 32 and 2048 DAC input clock cycles, depending

on the value of DIVSEL[2:0] (Register 0x0E, Bits[2:0]). The

frequency of the calibration clock should be between 0.5 MHz

and 4 MHz for reliable calibrations. Best results are obtained by

setting DIVSEL[2:0] to produce a calibration clock frequency

between these values. Separate self-calibration hardware is

included for each DAC. The DACs can be self-calibrated

individually or simultaneously.

To perform a device self-calibration, use the following procedure:

Write 0x00 to Register 0x12. This ensures that the UNCALI

and UNCALQ bits (Bit 1 and Bit 0) are reset.

Set up a calibration clock between 0.5 MHz and 4 MHz

using DIVSEL[2:0], and then enable the calibration clock

by setting the CALCLK bit (Register 0x0E, Bit 3).

Select the DAC(s) to self-calibrate by setting either Bit 4

(CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for

the Q DAC in Register 0x0E. Note that each DAC contains

independent calibration hardware so that they can be

calibrated simultaneously.

Start self-calibration by setting Bit 4 (CALEN) in Register 0x12.

Wait approximately 300 calibration clock cycles.

AD9115BCPZ Datasheet(PDF) 44 Page - Analog Devices

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