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XA Datasheet(PDF) 7 Page - Integrated Device Technology

Part # XA
Description  XA Family of Low Phase Noise Quartz-based PLL Oscillators
PDF  20 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

XA Datasheet(HTML) 7 Page - Integrated Device Technology

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©2018 Integrated Device Technology, Inc.
May 24, 2018
XA Datasheet
TJ
Total Jitter
LVDS.
—
23.6
—
ps
LVPECL.
—
27.7
—
LVCMOS.
FOUT = 125MHz.
—
19
—
fJITTER
Phase Jitter (12kHz–20MHz)
LVDS.
—
890
—
fs
LVPECL.
—
860
—
LVCMOS.
FOUT = 125MHz.
—
750
—
T a ble 1 0 . 2 .5 V AC Ele c t ric a l Cha ra c t e rist ic s
VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
Minimum
Typical
Maximum
Units
F
Output Frequency Range
LVDS.
0.75
—
1000
MHz
LVPECL.
0.75
—
1000
LVCMOS.
0.75
—
180
Frequency Stability
Temperature = -40°C to +85°C.
±25
—
±100
ppm
Temperature = -40°C to +105°C.
±50
—
±100
ppm
Aging (1st year)
TA = 25°C.
—
—
±3
ppm
Aging (10 years)
TA = 25°C.
—
—
±10
ppm
Output Load
LVDS.
Differential.
—
100
—
Ω
LVPECL.
VDD - 2.0V.
—
50
—
LVCMOS.
To GND.
—
15
—
pF
TST
Start-up Time
Output valid time after VDD meets minimum
specified level.
——
10
ms
tR
Output Rise Time
LVDS.
20% to 80% Vpp.
——
400
ps
LVPECL.
—
—
400
LVCMOS.
10% to 90% VDD.
——
3.5
ns
tF
Output Fall Time
LVDS.
80% to 20% Vpp.
——
400
ps
LVPECL.
—
—
400
LVCMOS.
90% to 10% VDD.
——
3
ns
ODC
Output Clock Duty Cycle
LVDS.
45
—
55
%
LVPECL.
45
—
55
LVCMOS.
45
—
55
TOE
Output Enable/ Disable Time
—
—
—
100
ns
T a ble 9 . 3 .3 V AC Ele c t ric a l Cha ra c t e rist ic s (Cont .)
VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
Minimum
Typical
Maximum
Units



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