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XRT71D04

4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

REV. 1.1.1

8

66

MCLK_1

I

Master Clock Input - channel 1:

See description of pin 26.

Internal 50 K Ohm pull-up resistor.

67

GND

****

Digital Ground

68

RCLK_1

I

Received Clock (Jittery) - channel 1:

See description of pin 28.

Internal 50 K Ohm pull-up resistor.

69

RPOS_1

I

Received Positive Data (Jittery) Input: - channel 1:

See description of pin 29.

Internal 50 K Ohm pull-up resistor.

70

RNEG_1

I

Received Negative Data (Jittery) - channel 1:

See description of pin 30.

Internal 50 K Ohm pull-up resistor.

71

VDD

****

Digital Power Supply = 5V±5% or 3.3V±5%

72

RNEG_0

I

Received Negative Data (Jittery) - channel 0:

See description of pin 30.

Internal 50 K Ohm pull-up resistor.

73

RPOS_0

I

Received Positive Data (Jittery) Input: - channel 0:

See description of pin 29.

Internal 50 K Ohm pull-up resistor.

74

RCLK_0

I

Received Clock (Jittery) - channel 0:

See description of pin 28.

Internal 50 K Ohm pull-up resistor.

75

GND

****

Digital Ground

76

MCLK_0

I

Master Clock Input - channel 0:

See description of pin 26.

Internal 50 K Ohm pull-up resistor.

77

DJA_1/SDI

I

Harware Mode

Disable Jitter Attenuator Input - Channel 1:

See description of pin 25

Host Mode

Serial Data Input

The address value (of the command registers) or the data value is either Read or

Written through this pin.

The input data will be sampled on the rising edge of the SCLK pin.

Internal 50 K Ohm pull-down resistor.

78

STS1_3

I

SONET STS1 Mode Select - channel 3:

See description of pin 23

79

FL_3

O

FIFO Limit - channel 3:

See description of pin 22

80

AGND

****

Analog Ground

PIN DESCRIPTION