AD5686 datasheet(6/27 Pages) AD

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AD5686/AD5684

Data Sheet

Rev. C | Page 6 of 27

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.

VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 4.

1.62 V ≤ VLOGIC <

2.7 V

2.7 V ≤ VLOGIC ≤

5.5 V

Parameter1

Symbol

Min

Max

Min

Max

Unit

SCLK Cycle Time

SCLK High Time

SCLK Low Time

SYNC to SCLK Falling Edge Setup Time

Data Setup Time

Data Hold Time

SCLK Falling Edge to SYNC Rising Edge

Minimum SYNC High Time

SYNC Rising Edge to SYNC Rising Edge (DAC Register Update/s)

870

830

SYNC Falling Edge to SCLK Fall Ignore

t10

LDAC Pulse Width Low

t11

SYNC Rising Edge to LDAC Rising Edge

t12

SYNC Rising Edge to LDAC Falling Edge

t13

LDAC Falling Edge to SYNC Rising Edge

t14

840

800

Minimum Pulse Width Low

t15

Pulse Activation Time

t16

Power-Up Time2

4.5

µs

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.

Time to exit power-down to normal mode of AD5686/AD5684 operation, SYNC rising edge to 90% of DAC midscale value, with output unloaded.

SCLK

SYNC

SDIN

DB23

t10

t11

t12

LDAC1

LDAC2

t13

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

RESET

t15

t16

VOUT

DB0

t14

Figure 2. Serial Write Operation

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