AD5686R datasheet(22/31 Pages) AD

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AD5686R/AD5685R/AD5684R

Data Sheet

Rev. D | Page 22 of 31

23B

STANDALONE OPERATION

The write sequence begins by bringing the

SYNCE

line low. Data

from the SDIN line is clocked into the 24-bit input shift register

on the falling edge of SCLK. After the last of 24 data bits is

clocked in,

SYNCE

should be brought high. The programmed

function is then executed, that is, an

LDACE

-dependent change

in DAC register contents and/or a change in the mode of

operation. If

SYNCE

is taken high at a clock before the 24th clock,

it is considered a valid frame and invalid data may be loaded to

the DAC.

SYNCE

must be brought high for a minimum of

20 ns (single channel, see t8 in Figure 2) before the next write

sequence so that a falling edge of

SYNCE

can initiate the next

write sequence.

SYNCE

should be idled at rails between write

sequences for even lower power operation of the part.

The

SYNCE

line is kept low for 24 falling edges of SCLK, and the

DAC is updated on the rising edge of

SYNCE

When the data has been transferred into the input register of

the addressed DAC, all DAC registers and outputs can be

updated by taking

LDACE

low while the

SYNCE

line is high.

24B

WRITE AND UPDATE COMMANDS

46B

Write to Input Register n (Dependent on

LDACE

)

Command 0001 allows the user to write to each DAC’s

dedicated input register individually. When

LDACE

is low,

the input register is transparent (if not controlled by the

LDACE

mask register).

47B

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers/outputs with the

contents of the input registers selected and updates the DAC

outputs directly.

48B

Write to and Update DAC Channel n (Independent

LDACE

)

Command 0011 allows the user to write to the DAC registers

and update the DAC outputs directly.

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