AD8021 datasheet(23/32 Pages) AD

23 / 32 page

AD5429/AD5439/AD5449

Rev. 0 | Page 23 of 32

MC68HC11 to AD5429/AD5439/AD5449 Interface

Figure 50 is an example of a serial interface between the DAC

and the MC68HC11 microcontroller. The serial peripheral

interface (SPI) on the MC68HC11 is configured for master

mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the

clock phase bit (CPHA) = 1. The SPI is configured by writing

to the SPI control register (SPCR)—see the 68HC11 User

Manual. The SCK of the 68HC11 drives the SCLK of the DAC

interface; the MOSI output drives the serial data line (D

IN) of

the AD5429/AD5439/AD5449.

The SYNC signal is derived from a port line (PC7). When data

is being transmitted to the AD5429/AD5439/AD5449, the

SYNC line is taken low (PC7). Data appearing on the MOSI

output is valid on the falling edge of SCK. Serial data from the

68HC11 is transmitted in 8-bit bytes with only 8 falling clock

edges occurring in the transmit cycle. Data is transmitted MSB

first. To load data to the DAC, PC7 is left low after the first eight

bits are transferred, and a second serial write operation is

performed to the DAC. PC7 is taken high at the end of this

procedure.

SCLK

SCK

AD5429/AD5439/

AD5449*

SYNC

PC7

SDIN

MOSI

MC68HC11*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 50. MCH68HC11/68L11 to AD5429/AD5439/AD5449 Interface

If the user wants to verify the data previously written to the

input shift register, the SDO line can be connected to MISO of

the MC68HC11, and, with SYNC low, the shift register clocks

data out on the rising edges of SCLK.

MICROWIRE to AD5429/AD5439/AD5449 Interface

Figure 51 shows an interface between the DAC and any

MICROWIRE compatible device. Serial data is shifted out on

the falling edge of the serial clock, SK, and is clocked into the

DAC input shift register on the rising edge of SK, which

corresponds to the falling edge of the DAC’s SCLK.

SCLK

MICROWIRE*

SYNC

SDIN

AD5429/AD5439/

AD5449*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 51. MICROWIRE to AD5429/AD5439/AD5449 Interface

PIC16C6x/7x to AD5429/AD5439/AD5449

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit (CKP) = 0. This is

done by writing to the synchronous serial port control register

(SSPCON). See the PIC16/17 Microcontroller User Manual.

In this example, the I/O port RA1 is used to provide a SYNC

signal and enable the serial port of the DAC. This micro-

controller transfers only eight bits of data during each serial

transfer operation; therefore, two consecutive write operations

are required. Figure 52 shows the connection diagram.

SCLK

SCK/RC3

PIC16C6x/7x*

SYNC

RA1

SDIN

SDI/RC4

AD5429/AD5439/

AD5449*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 52. PIC16C6x/7x to AD5429/AD5439/AD5449 Interface

AD8021 Datasheet(PDF) 23 Page - Analog Devices

AD8021 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL