AD5044 datasheet(5/28 Pages) AD

5 / 28 page

Data Sheet

AD5024/AD5044/AD5064

Rev. G | Page 5 of 28

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and

Figure 5. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 4.

Parameter1

Symbol

Min

Typ

Max

Unit

SCLK Cycle Time

SCLK High Time

SCLK Low Time

SYNC to SCLK Falling Edge Setup Time

Data Setup Time

Data Hold Time

SCLK Falling Edge to SYNC Rising Edge

Minimum SYNC High Time (Single Channel Update)

μs

Minimum SYNC High Time (All Channel Update)

μs

SYNC Rising Edge to SCLK Fall Ignore

LDAC Pulse Width Low

t10

SCLK Falling Edge to LDAC Rising Edge

t11

CLR Minimum Pulse Width Low

t12

SCLK Falling Edge to LDAC Falling Edge

t13

CLR Pulse Activation Time

t14

10.6

μs

SCLK Rising Edge to SDO Valid

t152, 3

SCLK Falling Edge to SYNC Rising Edge

t162

SYNC Rising Edge to SCLK Rising Edge

t172

SYNC Rising Edge to LDAC/CLR Falling Edge (Single Channel Update)

t182

μs

SYNC Rising Edge to LDAC/CLR Falling Edge (All Channel Update)

t182

μs

Power-up Time4

4.5

μs

1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.

2 Daisy-chain mode only.

3 Measured with the load circuit of Figure 3. t15 determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only.

4 Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32nd clock edge to 90% of DAC midscale value, with output unloaded.

Circuit and Timing Diagrams

2mA

IOL

2mA

IOH

TO OUTPUT

50pF

VOH (MIN) + VOL (MAX)

Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications

AD5044 Datasheet(PDF) 5 Page - Analog Devices

AD5044 Datasheet(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL