AD5044 datasheet(25/28 Pages) AD

25 / 28 page

Data Sheet

AD5024/AD5044/AD5064

Rev. G | Page 25 of 28

MICROPROCESSOR INTERFACING

AD5024/AD5044/AD5064/AD5064-1 to Blackfin

ADSP-BF527 Interface

Figure 52 shows a serial interface between the AD5024/

AD5044/AD5064/AD5064-1 and the Blackfin® ADSP-BF527

microprocessor. The ADSP-BF527 processor incorporates two

dual-channel synchronous serial ports, SPORT1 and SPORT0, for

serial and multiprocessor communications. Using SPORT0 to

connect to the AD5024/AD5044/AD5064/AD5064-1, the setup

for the interface is as follows: DT0PRI drives the DIN pin of the

AD5024/AD5044/AD5064/AD5064-1, and TSCLK0 drives the

SCLK of the devices. The SYNC pin is driven from TFS0.

AD5024/

AD5044/

AD5064/

AD5064-1*

ADSP-BF527*

*ADDITIONAL PINS OMITTED FOR CLARITY.

SYNC

TFS0

DIN

DT0PRI

SCLK

TSCLK0

Figure 52. AD5024/AD5044/AD5064/AD5064-1 to Blackfin

ADSP-BF527 Interface

AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11

Interface

Figure 53 shows a serial interface between the AD5024/AD5044/

AD5064/AD5064-1 and the 68HC11/68L11 microcontroller.

SCK of the 68HC11/68L11 drives the SCLK of the AD5024/

AD5044/AD5064/AD5064-1, and the MOSI output drives the

serial data line of the DAC.

AD5024/

AD5044/

AD5064/

AD5064-1*

68HC11/68L11*

*ADDITIONAL PINS OMITTED FOR CLARITY.

SYNC

PC7

SCLK

SCK

DIN

MOSI

Figure 53. AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 Interface

The SYNC signal is derived from a port line (PC7). The setup

conditions for correct operation of this interface are as follows:

The 68HC11/68L11 is configured with its CPOL bit as 0, and its

CPHA bit as 1. When data is being transmitted to the DAC, the

SYNC line is taken low (PC7). When the 68HC11/68L11 is

configured as described previously, data appearing on the MOSI

output is valid on the falling edge of SCK. Serial data from the

68HC11/68L11 is transmitted in 8-bit bytes with only eight

falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. To load data to the AD5024/AD5044/

AD5064, PC7 is left low after the first eight bits are transferred,

and a second serial write operation is performed to the DAC.

PC7 is taken high at the end of this procedure.

AD5024/AD5044/AD5064/AD5064-1 to 80C51/80L51

Interface

Figure 54 shows a serial interface between the AD5024/AD5044/

AD5064/AD5064-1 and the 80C51/80L51 microcontroller. The

setup for the interface is as follows: TxD of the 80C51/80L51

drives SCLK of the AD5024/AD5044/AD5064/AD5064-1, and

RxD drives the serial data line of the device. The SYNC signal is

again derived from a bit-programmable pin on the port. In this

case, Port Line P3.3 is used. When data is to be transmitted to the

AD5024/AD5044/AD5064/AD5064-1, P3.3 is taken low. The

80C51/80L51 transmit data in 8-bit bytes only; thus, only eight

falling clock edges occur in the transmit cycle. To load data to

the DAC, P3.3 is left low after the first eight bits are transmitted,

and a second write cycle is initiated to transmit the second byte of

data. P3.3 is taken high following the completion of this cycle.

The 80C51/80L51 output the serial data in a format that has the

LSB first. The AD5024/AD5044/AD5064/AD5064-1 must

receive data with the MSB first. The 80C51/80L51 transmit

routine should take this into account.

AD5024/

AD5044/

AD5064/

AD5064-1*

*ADDITIONAL PINS OMITTED FOR CLARITY.

DIN

RxD

SYNC

P3.3

80C51/80L51*

SCLK

TxD

Figure 54. AD5024/AD5044/AD5064/AD5064-1 to 80C512/80L51 Interface

AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE

Interface

Figure 55 shows an interface between the AD5024/AD5044/

AD5064/AD5064-1 and any MICROWIRE-compatible device.

Serial data is shifted out on the falling edge of the serial clock and is

clocked into the AD5024/AD5044/AD5064/AD5064-1 on the

rising edge of the SCLK.

AD5024/

AD5044/

AD5064/

AD5064-1*

*ADDITIONAL PINS OMITTED FOR CLARITY.

SCLK

SYNC

MICROWIRE*

DIN

Figure 55. AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE Interface

AD5044 Datasheet(PDF) 25 Page - Analog Devices

AD5044 Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL