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AD5405

Data Sheet

Rev. D | Page 18 of 24

PARALLEL INTERFACE

Data is loaded into the AD5405 in a 12-bit parallel word format.

Control lines CS and R/W allow data to be written to or read from

the DAC register. A write event takes place when CS and R/W

are brought low, data available on the data lines fills the shift

the latched data-word to the DAC register. The DAC latches are

not transparent; therefore, a write sequence must consist of a

falling and rising edge on CS to ensure that data is loaded into

the DAC register and that its analog equivalent is reflected on

the DAC output. A read event takes place when R/W is held high

and CS is brought low. Data is loaded from the DAC register, goes

back into the input register, and is output onto the data line, where

it can be read back to the controller for verification or diagnostic

purposes. The input and DAC registers of these devices are not

transparent; therefore, a falling and rising edge of CS is required

to load each data-word.

MICROPROCESSOR INTERFACING

ADSP-21xx Processors to AD5405 Interface

Figure 37 shows the AD5405 interfaced to the ADSP-21xx series

of DSPs as a memory-mapped device. A single wait state may be

necessary to interface the AD5405 to the ADSP-21xx, depending

on the clock speed of the DSP. The wait state can be programmed

via the data memory wait state control register of the ADSP-21xx

(see the ADSP-21xx family user manual for details).

R/W

DB0 TO DB11

AD54051

ADDRESS

DECODER

DATA 0 TO

DATA 23

ADDRESS BUS

ADDR0 TO

ADRR13

ADSP-21xx1

DATA BUS

DMS

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 37. ADSP-21xx to AD5405 Interface

8xC51 to AD5405 Interface

Figure 38 shows the interface between the AD5405 and the

8xC51 family of DSPs. To facilitate external data memory access,

the address latch enable (ALE) mode is enabled. The low byte of

the address is latched with this output pulse during access to the

external memory. AD0 to AD7 are the multiplexed low order

addresses and data bus; they require strong internal pull-ups when

emitting 1s. During access to external memory, A8 to A15 are

the high order address bytes. Because these ports are open

drained, they also require strong internal pull-ups when

emitting 1s.

R/W

DB0 TO DB11

AD54051

ADDRESS

DECODER

AD0 TO AD7

ADDRESS BUS

A8 TO A15

80511

DATA BUS

1ADDITIONAL PINS OMITTED FOR CLARITY.

8-BIT

LATCH

ALE

Figure 38. 8xC51 to AD5405 Interface

ADSP-BF504 to ADSP-BF592 Device Family to AD5405

Interface

Figure 39 shows a typical interface between the AD5405 and the

ADSP-BF504 to ADSP-BF592 family of DSPs. The asynchronous

memory write cycle of the processor drives the digital inputs of

the DAC. The AMSx line is actually four memory select lines.

Internal ADDR lines are decoded into AMS3–0; these lines are

then inserted as chip selects. The rest of the interface is a

standard handshaking operation.

R/W

DB0 TO DB11

AD54051

ADDRESS

DECODER

DATA 0 TO

DATA 23

ADDRESS BUS

ADDR1 TO

ADRR19

ADSP-BF5xx1

DATA BUS

AMSx

AWE

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 39. ADSP-BF504 to ADSP-BF592 Device Family to AD5405 Interface

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