AD5405 datasheet(19/24 Pages) AD

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Data Sheet

AD5405

Rev. D | Page 19 of 24

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration of

the power supply and ground return layout helps to ensure the

rated performance. The PCB on which the AD5405 is mounted

must be designed so the analog and digital sections are separated

and confined to certain areas of the board. If the DAC is in a system

where multiple devices require an AGND to DGND connection,

the connection must be made at one point only. The star ground

point must be established as close as possible to the device.

These DACs must have ample supply bypassing of 10 µF in parallel

with 0.1 µF on the supply located as close as possible to the

package, ideally right up against the device. The 0.1 µF capacitor

must have low effective series resistance (ESR) and low effective

series inductance (ESI), like the common ceramic types of cap-

acitors that provide a low impedance path to ground at high

frequencies, to handle transient currents due to internal logic

switching. Low ESR 1 µF to 10 µF tantalum or electrolytic

capacitors must also be applied at the supplies to minimize

transient disturbance and filter out low frequency ripple.

Components, such as clocks, that produce fast switching signals

must be shielded with digital ground to avoid radiating noise to

other parts of the board, and they must never run near the

reference inputs.

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board must run at right angles to each

other. This reduces the effects of feedthrough on the board.

A microstrip technique is by far the best, but its use is not

always possible with a double-sided board. In this technique,

the component side of the board is dedicated to the ground

plane, and signal traces are placed on the soldered side.

It is good practice to use compact, minimum lead length PCB

layout design. Leads to the input must be as short as possible to

minimize IR drops and stray inductance.

The PCB metal traces between VREF and RFB must also be

matched to minimize gain error. To maximize high frequency

performance, the I-to-V amplifier must be located as close as

possible to the device.

Figure 40. Schematic of AD5405 Evaluation Board

AD5405 Datasheet(PDF) 19 Page - Analog Devices