DS3112 datasheet(91/135 Pages) DALLAS

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DS3112

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Transmit Operation

On reset, the transmit HDLC controller will flush the transmit FIFO and transmit an abort followed by

either 7Eh or FFh (depends on the setting of the TFS control bit) continuously. The transmit HDLC then

waits until there are at least two bytes in the transmit FIFO before beginning to send the packet. The

transmit HDLC will automatically add an opening flag of 7Eh to the beginning of the packet and zero

stuff the outgoing data stream. When the transmit HDLC controller detects that the TMEND bit in the

transmit FIFO is set, it will automatically calculate and add in the 16-bit CRC checksum followed by a

closing flag of 7Eh. If the FIFO is empty, then it will begin sending either 7Eh or FFh continuously. If

there is some more data in the FIFO, then the transmit HDLC will automatically add in the opening flag

and begin sending the next packet. Between consecutive packets, there are always at least two flags of

7Eh. If the transmit FIFO ever empties when a packet is being sent (i.e., before the TMEND bit is set),

then the transmit HDLC controller will send an abort of seven ones in a row (FEh) followed by a

continuous transmission of either 7Eh (flags) or FFh (idle) and the Transmit FIFO Underrun (TUDR)

status bit will be set. When the FIFO underruns, the transmit HDLC controller should be reset by the host.

The transmit HDLC has been designed to minimize its real-time host support requirements. The transmit

FIFO is 256 bytes, which is deep enough to store the three T3 packets (Path ID, Idle Signal ID, and Test

Signal ID) that need to be sent once a second. Hence in T3 applications, the host only needs to access the

transmit HDLC once a second to load up the three messages. Once the host has loaded an outgoing

packet, it can monitor the Transmit Packet End (TEND) status bit to know when the packet has finished

being transmitted. Also, the host can be notified when the FIFO has emptied below a programmable level

called the low watermark. The host must never overfill the FIFO. To keep this from occurring, the host

can obtain the real- time depth of the transmit FIFO via the Transmit FIFO Level bits in the HDLC Status

9.2 HDLC Control and FIFO Register Description

HCR

HDLC Control Register

80h

Bit #

Name

n/a

RHR

THR

TFS

n/a

TCRCI

TZSD

TCRCD

Default

Bit #

Name

RHWMS2

RHWMS1

RHWMS0

TLWMS2

TLWMS1

TLWMS0

RID

TID

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Transmit CRC Defeat (TCRCD). When this bit is set low, the HDLC will automatically calculate

and append the 16-bit CRC to the outgoing HDLC message. When this bit is set high, the device will not

append the CRC to the outgoing message.

0 = enable CRC generation (normal operation)

1 = disable CRC generation

DS3112 Datasheet(PDF) 91 Page - Dallas Semiconductor

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