DS3112 datasheet(11/135 Pages) DALLAS

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DS3112

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2. SIGNAL DESCRIPTION

2.1 Overview/Signal Pin List

This section describes the input and output signals on the DS3112. Signal names follow a convention that

is shown in Table 2.1A. Table 2.1B lists all of the signals, their signal type, description, and pin location.

Symbols appended with an asterisks (*) are active low signals. The absence of an asterisks implies an

active high signal.

SIGNAL NAMING CONVENTION Table 2.1A

FIRST LETTERS

SIGNAL CATEGORY

SECTION

CPU/Host Control Access Port

2.2

T3/E3 Receive Framer

2.3

T3/E3 Transmit Formatter

2.4

Low Speed (T1 or E1) Receive Port

2.5

Low Speed (T1 or E1) Transmit Port

2.6

High Speed (T3 or E3) Receive Port

2.7

High Speed (T3 or E3) Transmit Port

2.8

JTAG Test Port

2.9

SIGNAL DESCRIPTION/PIN LIST Table 2.1B

SYMBOL

TYPE

SIGNAL DESCRIPTION

CALE

CPU Bus Address Latch Enable.

CA0

CPU Bus Address Bit 0. LSB.

CA1

CPU Bus Address Bit 1.

CA2

CPU Bus Address Bit 2.

CA3

CPU Bus Address Bit 3.

CA4

CPU Bus Address Bit 4.

CA5

CPU Bus Address Bit 5.

CA6

CPU Bus Address Bit 6.

CA7

CPU Bus Address Bit 7. MSB.

CCS*

CPU Bus Chip Select.

CD0

I/O

CPU Bus Data Bit 0. LSB.

CD1

I/O

CPU Bus Data Bit 1.

CD2

I/O

CPU Bus Data Bit 2.

CD3

I/O

CPU Bus Data Bit 3.

CD4

I/O

CPU Bus Data Bit 4.

CD5

I/O

CPU Bus Data Bit 5.

CD6

I/O

CPU Bus Data Bit 6.

CD7

I/O

CPU Bus Data Bit 7.

CD8

I/O

CPU Bus Data Bit 8.

CD9

I/O

CPU Bus Data Bit 9.

CD10

I/O

CPU Bus Data Bit 10.

CD11

I/O

CPU Bus Data Bit 11.

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