FPD85308 datasheet(10/31 Pages) NSC

10 / 31 page

Functional Description (Continued)

White Data

The White Data function generates all “1” data beginning at

line 769 and continuing until the beginning of the next frame.

This function is controlled via D6 Register Bit 7.

Timing Control

The Timing Control function generates control to column

drivers, row drivers, and power supply. The programmable

GPOs provide for CD latch pulse, REV, and gate driver

control generation. The GPOs allow the user to generate

control anywhere within the frame data. Standard gate driver

interface or custom gate interfaces can be implemented with

the nine GPOs. Note that GPO [8] must be used for output

blanking control.

Five registers provide the timing definition for each GPO.

The Horizontal Start register defines the output pixel number

for which the GPO output goes active. The Horizontal dura-

tion register determines how many clocks the output will

remain active during the line. The Vertical Start register

defines at what line # the output becomes active, and the

Vertical duration register defines how many lines the output

remains active. Each output has a control register (bit 0)

which defines the GPO polarity (active high or low). Another

bit in the control register (bit 1) enables the “toggle” mode.

This mode is useful in REV generation when alternating

polarity is required from line to line. Frame to Frame polarity

changes are made by programming an odd # in the vertical

duration register when in “toggle” mode. Please note that

ODD Frame size inputs are not supported in ’’toggle mode’’

function.

Two of the General Purpose Outputs have additional capa-

bilities. GPO [8] controls output blanking and must be used

for this purpose. If output blanking is not desired, this register

must be programmed to always be active. White data gen-

eration (all “1” data) at the end of each frame is generated

when D6 register bit 7 is set. When this bit is set, white data

is output after line #768 if GPO [8] is active. GPO [0] is

capable of performing line inversion on the output data. Bits

[5:3] of the Output Format Control register provides control

for this function.

See

APPENDIX A: GPO Programming Examples.

SERIAL EEPROM INTERFACE

The Serial EEPROM Interface controls the FPD85308 initial-

ization. If the EEPROM is not present (EESD and EESC are

pulled high), or if EEPROM address 80H is not “00”, the

internal default values are used to initialize all programmable

functions of the FPD85308.

At power-up, the FPD85308 configures the internal program-

mable registers with data from the EEPROM. After the

FPD85308 is initialized, the EEPROM can be accessed by

the system in which display configuration and manufacturing

information can be obtained. The EEPROM can be pro-

grammed “in system” providing quick evaluation of different

display timing.

External access to the EEPROM must be preceded by ap-

plying a “1” to pin TEST [2] in order to interrupt the

FPD85308 download.

The FPD85308 initialization data begins at EEPROM ad-

dress 80H. The first 128 bytes (0-7F) are reserved for dis-

play identification data.

A power-up delay can be programmed using bits [6:5] of the

Input Format Control Register. This delays outputting (driv-

ing) of the data and control for up to 5 frame times after

reset. The TEST [2] pin must be low for a power-up delay to

occur.

VERTICAL/HORIZONTAL REFERENCE GENERATOR

This block provides Vertical and Horizontal Reference points

for the Timing Control Function. VSYNC, HSYNC and ENAB

along with programmable control from the input control reg-

ister bits 0 and 1 (FIX HORIZONTAL and FIX VERTICAL)

are used to determine when the video from the host is valid.

Three input modes are supported. See

Table 1.

Fixed Vertical, Fixed Horizontal

The horizontal timing is fixed and determined by the Hori-

zontal Backporch register. The vertical timing is also fixed

and determined by the Vertical Backporch register. ENAB is

ignored and is not necessary.

Fixed Vertical, ENAB Controlled Horizontal

The horizontal timing is controlled by the ENAB timing. The

vertical timing is fixed and determined by the Vertical Back-

porch register and HSYNC input.

ENAB Only

In ENAB Only timing, VSYNC and HSYNC are ignored. All

timing is derived from the ENAB signal.

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