PCA9535E, PCA9535EC

www.onsemi.com

12

Figure 8. Read from Register

Remark: Transfer can be stopped at any time by a STOP condition.

A

S

START condition

R/W

acknowledge

from slave

A

acknowledge

from slave

SDA

AP

acknowledge

from master

DATA (first byte)

slave address

STOP

condition

S

(repeated)

START condition

(cont.)

(cont.)

A2 A1 A0

1A

A6

R/W

acknowledge

from slave

slave address

at this moment master−transmitter becomes master−receiver

and slave−receiver becomes slave−transmitter

NA

no acknowledge

from master

COMMAND BYTE

A2 A1 A0

A6

0

data from lower or

upper byte of register

LSB

MSB

DATA (last byte)

data from upper or

lower byte of register

LSB

MSB

A5 A4 A3

A5 A4 A3

Figure 9. Read from Input Port Register, Scenario 1

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge

phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).

A2 A1 A0 1 A

S A6

START condition

R/W

acknowledge

from slave

A

SCL

SDA

A

read from port 0

P

9

8

7

6

5

4

3

2

1

I0.x

slave address

7

STOP condition

acknowledge

from master

A

I1.x

7

acknowledge

from master

A

I0.x

7

acknowledge

from master

1

I1.x

7

non acknowledge

from master

data into port 0

read from port 1

data into port 1

INT

A5 A4 A3

654

32 1 0

654

32 1 0

65 4

3 2 1 0

654

32 1 0

Figure 10. Read from Input Port Register, Scenario 2

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge

phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).

A2 A1 A0 1 A

S A6

START condition

R/W

acknowledge

from slave

A

SCL

SDA

A

read from port 0

P

9

8

7

6

5

4

3

2

1

I0.x

slave address

STOP condition

acknowledge

from master

A

I1.x

acknowledge

from master

A

I0.x

acknowledge

from master

1

I1.x

non acknowledge

from master

data into port 0

read from port 1

data into port 1

INT

2

1

A

T

A

D

3

0

A

T

A

D

0

1

A

T

A

D

0

0

A

T

A

D

DATA 00

DATA 01

DATA 02

DATA 03

2

1

A

T

A

D

1

1

A

T

A

D

0

1

A

T

A

D

A5A4 A3