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DLPR410 Datasheet(PDF) 8 Page - Texas Instruments |
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DLPR410 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 17 page ![]() DLPR410 TCK TDI TMS OE/RESET CLKOUT CE CF EN_EXT_SEL REV_SEL0 REV_SEL1 D0 TDO CEO 8 DLPR410 DLPS027E – AUGUST 2012 – REVISED DECEMBER 2018 www.ti.com Product Folder Links: DLPR410 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The configuration bit stream stored in the DLPR410 device supports reliable operation of the DLPC410 device with the DLP650LNIR, DLP7000, DLP7000UV, DLP9500, and DLP9500UV DMDs. The DLPC410 digital controller loads this configuration bit stream from the DLPR410 device. 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Data Interface 8.3.1.1 Data Outputs The DLPR410 device s configured for serial mode operation, where D0 is the data output pin. D0 output pin provides a serial connection to the DLPC410, where the configuration is read out by the DLPC410. 8.3.1.2 Configuration Clock Input The configuration CLK is connected to the DLPC410 in Master Serial mode, where the DLPC410 provides the clock pulses to read the configuration from the DLPR410 device. 8.3.1.3 Output Enable and Reset When the OE/RESET input is held low, the address counter is reset and the Data and CLKOUT outputs are placed in high-impedance state. OE/RESET must be pulled High using an external 4.7-kΩ pull-up to VCCO. |
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