Conceptual

uP6019

12

uP6019-DS-C3101, Oct. 2017

www.upi-semi.com

Application Information

Layout Consideration

For best performance of the uP6019, the following guidelines are recommended.

1. Input and output capacitors should be placed close to the IC and connected to ground plane to reduce noise coupling.

2. The GND should be connected to a strong ground plane for heat sinking and noise protection.

3. Keep the main current traces as short and wide as possible.

4. LX node of DC-DC converter is with high frequency voltage swing. To prevent radiation of high frequency noise, the inductor

should be placed close to the IC.

5. Please keep VIN, FB, LGRIP and OCP trace away from the noise source such as LX node and place CVIN close to the IC

and connected to ground plane to reduce supply ripple.

6. Place the feedback components as close as possible to the IC and keep away from the noise source.

7. Since the uP6019 is high performance converter and also running high currents, the layout should be consideration of the

thermal as well. A thermal pad improves the thermal capabilities of the package, please soldered exposed pad to the large

plate.

8. The exposed pad II(VOUT) have the most heating of the IC (shown as figure1), please increase VOUT copper plane as

wide as possible to get better thermal performance.

GND

VOUT

GND

GND

GND

Inductor

VIN

Via for VIN

Via for GND

Via for VOUT

Via for LGRIP_R

Via for VDD

FB

EN

25

23

26

VREG

LGRIP

22

NC

VIN

OCP

21

20

PGND

PGND

PGND

PGND

PGND

LX_C

BOOT

24

27

Exposed Pad I

(LX)

28

Exposed Pad II

(VOUT)

13

12

11

10

9

7

8

WQFN4x4-26L

Via for LGRIP_R

Figure 1. Layout Reference of WQFN4x4-26WL