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MPC860SARPowerQUICC™TechnicalSummary

MOTOROLA

MPC860SAR PowerQUICC Features

In addition to ATM, the 860SAR also supports all of the performance and functionality of the MPC860MH,

including multichannel HDLC and Ethernet. This is because the CPM of the 860SAR is based on the CPM

of the MPC860MH. This enables the 860SAR to provide protocol processing (HDLC or transparent mode)

for time-division multiplexed channels. The only function missing is microcode support for some DSP

functions, which has been replaced with the ATM microcode.

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MPC860SAR PowerQUICC Features

The following list summarizes the key features of the MPC860SAR PowerQUICC:

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ATM support

— Compliant with ATM forum UNI 4.0 specification

— Cell processing up to 50–70 Mbps at 50-MHz system clock

— Cell multiplexing/demultiplexing

— Support of AAL5 and AAL0 protocols on a per-VC basis

– (AAL0 support enables OAM and software implementation of other protocols)

— ATM pace control (APC) scheduler, providing:

– Direct support of constant bit rate (CBR)

– Direct support of unspecified bit rate (UBR)

– Control mechanisms enabling software support of available bit rate (ABR)

— Support for two types of physical interfaces

– UTOPIA

– Byte-aligned serial (e.g. T1/E1/ADSL)

— UTOPIA-mode ATM supports:

– UTOPIA level 1 master with cell-level handshake

– Multi-PHY (up to 4 physical layer devices)

– Connection to 25 Mbps, 51 Mbps, or 155 Mbps framers

– UTOPIA clock rates of 1:2 or 1:3 system clock rates

— Serial-mode ATM connection supports:

– Transmission convergence (TC) function for T1/E1/ADSL lines

– Cell delineation

– Cell payload scrambling/descrambling

– Automatic idle/unassigned cell insertion/stripping

– Header error control (HEC) generation, checking, and statistics

– Glueless interface to Motorola CopperGold ADSL transceiver

— Receive VP/VC connection lookup mechanisms, including:

– Internal sequential lookup table supporting up to 32 connections

– Support for up to 64K connections using external memory via address compression or

content-addressable memory (CAM)

— Independent transmit/receive buffer descriptor ring data structures for each connection

— Interrupt report per channel using exception queue