AD5220 datasheet(4/16 Pages) AD

4 / 16 page

REV. B

–4–

AD5200/AD5201–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3])

Input Clock Pulsewidth

tCH, tCL

Clock Level High or Low

Data Setup Time

tDS

5ns

Data Hold Time

tDH

5ns

CS Setup Time

tCSS

CS High Pulsewidth

tCSW

CLK Fall to

CS Fall Hold Time

tCSH0

0ns

CLK Fall to

CS Rise Hold Time

tCSH1

0ns

CS Rise to Clock Rise Setup

tCS1

NOTES

1Typicals represent average readings at 25

°C and V

DD = 5 V, VSS = 0 V.

2Guaranteed by design and not subject to production test.

3See timing diagram for location of measured values. All input control voltages are specified with t

R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of

1.5 V. Switching characteristics are measured using VLOGIC = 5 V.

Specifications subject to change without notice.

(VDD = 5 V

10%, or 3 V

10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 C < TA < +85 C

unless otherwise noted.)

SDI

CLK

VOUT

DAC REGISTER LOAD

Figure 1a. AD5200 Timing Diagram

SDI

D4D3

D2D1

CLK

DAC REGISTER LOAD

VOUT

Figure 1b. AD5201 Timing Diagram

VDD

SDI

(DATA IN)

CLK

VOUT

CS1

CSW

CSH0

CSS

1LSB

CSH1

Figure 1c. Detail Timing Diagram

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