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DS3231 Datasheet(PDF) 16 Page - Dallas Semiconductor |
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DS3231 Datasheet(HTML) 16 Page - Dallas Semiconductor |
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16 / 19 page ![]() Figures 3 and 4 detail how data transfer is accom- plished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is trans- mitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all the serial clock puls- es and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most significant bit (MSB) first. The DS3231 can operate in the following two modes: Slave receiver mode (DS3231 write mode): Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recog- nized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS3231 address, which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte, the DS3231 outputs an Extremely Accurate I2C-Integrated RTC/TCXO/Crystal 16 ____________________________________________________________________ STOP CONDITION OR REPEATED START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED ACK START CONDITION ACK ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SLAVE ADDRESS MSB SCL SDA R/W DIRECTION BIT 12 6 7 8 9 1 2 8 9 3–7 Figure 2. I2C Data Transfer Overview A XXXXXXXX A 1101000 S 0 XXXXXXXX A XXXXXXXX A XXXXXXXX A P <SLAVE ADDRESS> S = START A = ACKNOWLEDGE P = STOP R/W = READ/WRITE OR DIRECTION BIT ADDRESS = D0H DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) <DATA (n + X)> <DATA (n + 1)> <DATA (n)> <WORD ADDRESS (n)> Figure 3. Slave Receiver Mode (Write Mode) A XXXXXXXX A 1101000 S 1 XXXXXXXX A XXXXXXXX A XXXXXXXX A P <SLAVE ADDRESS> S = START A = ACKNOWLEDGE P = STOP A = NOT ACKNOWLEDGE R/W = READ/WRITE OR DIRECTION BIT ADDRESS = D1H DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL <DATA (n + X)> <DATA (n + 2)> <DATA (n + 1)> <DATA (n)> Figure 4. Slave Transmitter Mode (Read Mode) |
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