FLEX10KE datasheet(2/100 Pages) ALTERA

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Altera Corporation

FLEX 10KE Embedded Programmable Logic Devices Data Sheet

Note to tables:

(1)

The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum

system gates.

(2)

New EPF10K100B designs should use EPF10K100E devices.

...and More

Features

–

Fabricated on an advanced process and operate with a 2.5-V

internal supply voltage

–

In-circuit reconfigurability (ICR) via external configuration

devices, intelligent controller, or JTAG port

–

ClockLockTM and ClockBoostTM options for reduced clock

delay/skew and clock multiplication

–

Built-in low-skew clock distribution trees

–100% functional testing of all devices; test vectors or scan chains

are not required

–

Pull-up on I/O pins before and during configuration

■

Flexible interconnect

–FastTrack® Interconnect continuous routing structure for fast,

predictable interconnect delays

–

Dedicated carry chain that implements arithmetic functions such

as fast adders, counters, and comparators (automatically used by

software tools and megafunctions)

–

Dedicated cascade chain that implements high-speed,

high-fan-in logic functions (automatically used by software tools

and megafunctions)

–

Tri-state emulation that implements internal tri-state buses

–

Up to six global clock signals and four global clear signals

■

Powerful I/O pins

–

Individual tri-state output enable control for each pin

–

Open-drain option on each I/O pin

–

Programmable output slew-rate control to reduce switching

noise

–Clamp to VCCIO user-selectable on a pin-by-pin basis

–

Supports hot-socketing

Table 2. FLEX 10KE Device Features

Feature

EPF10K100E (2)

EPF10K130E

EPF10K200E

EPF10K200S

Typical gates (1)

100,000

130,000

200,000

Maximum system gates

257,000

342,000

513,000

Logic elements (LEs)

4,992

6,656

9,984

EABs

Total RAM bits

49,152

65,536

98,304

Maximum user I/O pins

338

413

470

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