STV0974 datasheet(52/69 Pages) STMICROELECTRONICS

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STV0974

Functional description

4.9.3.4 Firmware patching

The STV0974 has some firmware patching capabilities addressable through I2C and

microprocessor interfaces through control registers firmware patch code downloads. Up to 15

different patches can be downloaded within a limit of 512 bytes of RAM.

The patch space starts from address 0x8600.

Patch structure:

“disable all patches”

“set address to patch”

“set offset of patch in memory”

“write patch in memory (starting from address 0x8600 + patch memory offset)”

“enable all patches”

The state in which to download the patch depends on the nature of the patch, most likely either idle

or sleep mode. Please contact ST support for patch delivery and recommendations for ideal use.

4.10

Additional features

There are a number of additional features which are supported by the STV0974, however

implementation of these features is not supported by this datasheet. Please contact the ST support

team for support of these features if you have a specific requirement.

● The polarity of the HSYNC and VSYNC signal can be programmed. However, these are non-

standard settings.

● The transmitted byte order of the RGB and YUV is programmable.

● The viewfinder color matrix can be programmed to match the characteristics of a local LCD

display.

Table 36 : Patch control registers

Name

Index

R/W

Format

default

Description

Patch enable

0x84BF

RRRR.RRDD

bit [1:0] = 01 patch enabled

bit [7:2] = 10 patch disabled

Patch address

0x8480

Ox8481

RRRR.RRRR

bit [15:0] = Reserved

Patch address delivered by ST

Patch memory

offset

0x84A0

0x84A1

1DDD.DDDD

DDDD.DDDD

bit [15] = 1

bit [14:0] = Patch memory offset

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