MSM6255 datasheet(26/39 Pages) OKI

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MSM6255

¡ Semiconductor

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CHφ

DIEN

display

RAM

OUT

CPU

LCDC

CPU

LCDC

CPU

LCDC

CPU

LCDC

fetching the

pattern data

tRAM

tUDS

tUDH

N + 1

M + 1

Fig. 10 Basic Timing of Synchronized Access to Display RAM

CL Q

DATA LATCH

M-WR

M-RD

DIEN

READY

V-RAM

SELECT

VDD

Fig. 11 Wait Function Controlling Circuit

Display RAM must meet the following condition:

TL > tRAM + tUDS

In writing data into the display RAM, LCDC should be synchronized so that the write pulse

occurs during the period of TC. In reading the pattern data from the CPU, the data of display RAM

should be latched first.

Figure 11 shows the controlling circuit.

Legend

: Period when the address bus is occupied by CPU

: Period when the LCDC fetches the refreshed data

tRAM

: Refresh address delay time + memory access time

tUDS

: Upper side data set-up time

tUDH

: Upper side data hold time

When DIEN is high, MA0 - MA15 output address to the upper side when CHf is low and to the

lower side when CHf is high.

To perform synchronized access method, the timing between DIEN and CHf should be as

described in Figure 10.

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