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AD1837AASZ Datasheet(PDF) 5 Page - Analog Devices

Part # AD1837AASZ
Description  2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
PDF  24 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD1837AASZ Datasheet(HTML) 5 Page - Analog Devices

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REV. A
–5–
AD1837A
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master, 48 kHz and 96 kHz)
tTBD
BCLK Delay
40
ns
From MCLK Rising Edge
tFSD
FSTDM Delay
5
ns
From BCLK Rising Edge
tTABDD
ASDATA Delay
10
ns
From BCLK Rising Edge
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling Edge
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling Edge
TDM256 MODE (Slave, 48 kHz and 96 kHz)
fAB
BCLK Frequency
256
fS
tTBCH
BCLK High
17
ns
tTBCL
BCLK Low
17
ns
tTFS
FSTDM Setup
10
ns
To BCLK Falling Edge
tTFH
FSTDM Hold
10
ns
From BCLK Falling Edge
tTBDD
ASDATA Delay
15
ns
From BCLK Rising Edge
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling Edge
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling Edge
TDM512 MODE (Master, 48 kHz)
tTBD
BCLK Delay
40
ns
From MCLK Rising Edge
tFSD
FSTDM Delay
5
ns
From BCLK Rising Edge
tTABDD
ASDATA Delay
10
ns
From BCLK Rising Edge
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling Edge
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling Edge
TDM512 MODE (Slave, 48 kHz)
fAB
BCLK Frequency
512
fS
tTBCH
BCLK High
17
ns
tTBCL
BCLK Low
17
ns
tTFS
FSTDM Setup
10
ns
To BCLK Falling Edge
tTFH
FSTDM Hold
10
ns
From BCLK Falling Edge
tTBDD
ASDATA Delay
15
ns
From BCLK Rising Edge
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling Edge
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling Edge
AUXILIARY INTERFACE (48 kHz and 96 kHz)
tAXDS
AAUXDATA Setup
10
ns
To AUXBCLK Rising Edge
tAXDH
AAUXDATA Hold
10
ns
From AUXBCLK Rising Edge
fABP
AUXBCLK Frequency
64
fS
Slave Mode
tAXBH
AUXBCLK High
15
ns
tAXBL
AUXBCLK Low
15
ns
tAXLS
AUXLRCLK Setup
10
ns
To AUXBCLK Rising Edge
tAXLH
AUXLRCLK Hold
10
ns
From AUXBCLK Rising Edge
Master Mode
tAUXLRCLK
AUXLRCLK Delay
15
ns
From AUXBCLK Falling Edge
tAUXBCLK
AUXBCLK Delay
20
ns
From MCLK Rising Edge
Specifications subject to change without notice.
MCLK
t
MH
PD/RST
t
ML
t
PDR
t
MCLK
Figure 1. MCLK and
PD/RST Timing



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