DSP56857 datasheet(312/662 Pages) FREESCALE

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Functional Description

5685X Digital Signal Controller User Manual, Rev. 4

12-12

Freescale Semiconductor

12.5.1.2 Normal Mode Receive

The conditions for data reception from the ESSI are as follows:

1. Set the SRXCR, SCR2, SCR3, and SCR4 registers to select Normal mode operation.

2. Define the receive clock.

3. Receive frame sync and frame structure required for proper system operation.

4. ESSI enabled (ESSIEN = 1)

5. Enable RXFIFO (RFEN=1) and configure Receive Watermark (RFWM = n) if RXFIFO is

used.

6. Enable receive interrupts.

7. Set the RE bit (RE = 1) to enable the receiver operation on the next frame sync boundary.

Table 12-6.

Normal Mode Transmit Operations

Step

TXFIFO Disabled1

TXFIFO Enabled

Rising edge of SC2. Note a word length frame

sync is shown. This only works if DC>0.

—

Data transferred to TXSR.

From STX

From TXFIFO

STD output pin is enabled2and the first bit of the

TXSR register appears on the output.

——

Flag status update.

The TDE bit is set

The TFE bit is set if the level of data in

the TXFIFO falls below the watermark

level.

If the TIE bit is set, enabling transmit interrupts,

then: Open options for processing the data

transfer is either polling or DMA transfers.

Transmit interrupt

occurs when TDE is

set.

Transmit interrupt occurs when TFE

set.

The TXSR is shifted on the next rising edge of

the SCK and the next bit appears on the STD

pin.

——

When WL bits (Section 11.8.14) have been sent

the STD is tri-stated.

——

Transmit underrun (setting the TUE bit of the

SSR register) is prevented by3:

New data is written

to the STX before

the TXSR tries to

obtain new transmit

data at the next

frame sync.

New data is written to the STX before

the TXSR tries to obtain data from an

empty TXFIFO (this can be several

frame times).

Repeat at step 1 on the next frame sync4.

——

See Figure 12-2.

The STD output signal is disabled except during the data transmission period.

Section 12.8.9 describes what happens when the TUE bit is set.

The frame sync must not occur earlier than it is configured in the STXCR as documented in Section 12.8.11.

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