DSP56857 datasheet(316/662 Pages) FREESCALE

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Functional Description

5685X Digital Signal Controller User Manual, Rev. 4

12-16

Freescale Semiconductor

The operation of clearing the TE bit disables the transmitter after completion of transmission of

the current data word. Setting the TE bit again enables transmission of the next word. During the

time TE = 0, the STD signal is tri-stated. The TE bit should be cleared after the TDE bit is set,

ensuring all pending data is transmitted.

Note:

In case of Normal mode with external frame sync, TE bit should be cleared after the

first bit of transmission only.

The Network mode transmitter generates interrupts every time slot (unless the TSM registers are

utilized) and requires the DSC program to respond to each time slot. These responses may be one

of the following:

•

Write the Data register with data to enable transmission in the next time slot.

•

Write the Time Slot register to disable transmission in the next time slot.

•

Do nothing—transmit underrun occurs at the beginning of the next time slot and the

previous data is re-transmitted.

Table 12-8.

Notes for Transmit Timing in Figure 12-5

Note

Source

Signal

Destination

Signal

Description

—

Example of a five time-slot frame, transmitting in time-slots 0 and 3.

2SC2

—

Example with word-length frame sync and standard timing (TFSI=0, TFSL=0,

and TEFS=0). Frame timing begins with the rising edge of SC2.

3—

TDE Status Flag

and Interrupt

This flag is set at the beginning of each word to indicate that another data

word should be supplied by the software. When the transmit interrupt is

enabled, the processor is interrupted to request the data. The flag and

interrupt are cleared when data is written to either the STX or STSR

registers.1

STX / STSR

TXSR

On each word clock boundary a decision is made concerning what to

transmit on the next time-slot.

If the STSR register was written during the previous time-slot the STD pin is

tri-stated.

If the STSR register was NOT written during the previous time-slot the

contents of the STX register is transferred to the TXSR register and this data

is shifted out. If the STX register has not been written in the previous

time-slot the previous data is reused.

If neither of these registers were written in the previous time-slot the TUE

status bit will be set and the hardware will operate as if the STX register had

been written. The STD pin will be enabled and the contents of the STX will

be transmitted again. This may lead to drive conflicts on the transmit data

line.

TXSR

STD Pin

On active time-slots, the TXSR register contents are shifted out on the STD

pin, one bit per rising edge of SCK.

On inactive time-slots, the STD pin is tri-stated so it can be driven by another

device.

Section 12.13 provides a complete description of interrupt processing.

DSP56857 Datasheet(PDF) 316 Page - Freescale Semiconductor, Inc

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