DSP56857 datasheet(318/662 Pages) FREESCALE

318 / 662 page

Functional Description

5685X Digital Signal Controller User Manual, Rev. 4

12-18

Freescale Semiconductor

An interrupt can occur after the reception of each data word or the programmer can poll the RDR

flag. The ESSI program response can be one of the following:

•

Read SRX and use the data

•

Read SRX and ignore the data

•

Do nothing—the receiver overrun exception occurs at the end of the current time slot.

12.5.3 Synchronous/Asynchronous Operating Modes

The transmit and receive sections of the ESSI may be synchronous or asynchronous. During

asynchronous operation the transmitter and receiver have their own separate clock and sync

signals. When operating in the Synchronous mode the transmitter and receiver use common clock

and synchronization signals, specified by the transmitter configuration. The SYN bit in SCR2

selects synchronous or asynchronous operation.

Since the ESSI is designed to operate either synchronously or asynchronously, separate receive

and transmit interrupts are provided. During the synchronous operation, the receiver and

transmitter operate in lock step with each other. Overhead may be reduced by eliminating either

the receive or transmit interrupts, driving both channels from the same set of interrupts. If this

decision is made, it is necessary to be aware of the specific timing of the receive and transmit

interrupts, because the interrupts are not generated at the same exact point in the frame timing,

Table 12-9.

Notes for Receive Timing in Figure 12-6

Note

Source Signal

Destination

Signal

Description

6—

—

Example of a five time slot frame, receiving data from time slots 0 and 2.

The receive hardware will obtain data on the SRD pin every bit time.

The software must determine which data belongs to each time slot and

discard the unwanted time slot data.

SC0

—

Receive clock timing from which it is derived.

8SC1

—

Example with bit length frame sync and standard timing (RFSI=0,

RFSL=1, and REFS=0). Frame timing begins with the rising edge of

SC1.

9SRD

RXSR

Data on the SRD pin is sampled on the falling edge of SC0 and shifted

into the RXSR register.

RXSR

SRX

At the word clock, the data in the RXSR register is transferred to the

SRX register.

RDR Status Flag

and Receive

Interrupt

—

This flag is set for each word clock (time slot) indicating data is available

to be processed. The software must keep track of the time slots as they

occur so it knows which data to keep.

If the receive interrupts are enabled (RIE=1) an interrupt will be

generated when this status flag is set. The software reads the SRX

Section 12.13 provides a complete description of the interrupt process.

DSP56857 Datasheet(PDF) 318 Page - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 318 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL