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UPD61052 Datasheet(PDF) 39 Page - NEC |
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UPD61052 Datasheet(HTML) 39 Page - NEC |
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39 / 106 page ![]() Data Sheet S15082EJ4V0DS 39 µPD61051, 61052 3.1 Register Mapping (General Mapping) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W 00H to 1FH Defined by firmware R/W 20H SI SSD SDI MSD MI SDW SDR R/W Download mode 21H SA19 to SA16 R/W Source address 22H SA15 to SA8 R/W Source address 23H SA7 to SA0 R/W Source address 24H DA16 R/W Destination address 25H DA15 to DA8 R/W Destination address 26H DA7 to DA0 R/W Destination address 27H TC18 to TC16 R/W Transfer data count 28H TC15 to TC8 R/W Transfer data count 29H TC7 to TC0 R/W Transfer data count 2AH iCPU-INT R/W Int. to internal CPU 2BH DMA- ERR-M DMA- RDY-M DMA- DONE-M R/W Interrupt mask0 2CH Defined by firmware R/W Interrupt mask1 2DH Defined by firmware R/W Interrupt mask2 2EH Defined by firmware R/W Interrupt mask3 2FH Defined by firmware R/W Interrupt mask4 30H DMA-ERR DMA-RDY DMA- DONE R/W Interrupt0 31H Defined by firmware R/W Interrupt1 32H Defined by firmware R/W Interrupt2 33H Defined by firmware R/W Interrupt3 34H Defined by firmware R/W Interrupt4 35H iROM2 to iROM0 R/W Mask ROM cycle 36H ISREQ OSVLD R/W Port setup 37H to 3DH 3EH NBR ALL RESET R/W Reset 3FH TD7 to TD0 R/W Transfer data |
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