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UPD61052 Datasheet(PDF) 13 Page - NEC |
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UPD61052 Datasheet(HTML) 13 Page - NEC |
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13 / 106 page ![]() Data Sheet S15082EJ4V0DS 13 µPD61051, 61052 (2) Instruction ROM interface Name IO Pin Number Function Active Polarity CA5 to CA0/ FA5 to FA0 O 187, 185 to 181 Address OS7 to OS0/ FA13 to FA6 O 65 to 63, 61, 59 to 56 Address OVOUT5 to OVOUT0/ FA19 to FA14 O 206 to 201 Address CD7 to CD0/ FD7 to FD0 I 172, 170 to 166, 164, 162 Data CWAIT/FOE O 161 Output enable L 1.9 Clock, Reset Name IO Pin Number Function Active Polarity SCLK I 28 System clock ↑ STCLK I 34 System time clock ↑ PSTOP I 29 Internal PLL operation control L: Normal, H: Internal PLL stop H PWM O 40 PWM output RESET I 151 Reset L 1.10 N-Wire IE Port for firmware of Internal CPU evaluation When not connecting an in-circuit emulator, take countermeasures against noise by pulling up the NDI pin to avoid the pin becoming low level. Name IO Pin Number Function Active Polarity NMOD I 178 Pin used when connecting IE Pull up when connecting IE H NCLK I 174 Serial clock ↑ NRST I 176 N-wire reset L NDI I 179 Data input NDO O 180 Data output |
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