VT6212 datasheet(21/26 Pages) VIA

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VT6212 / VT6212L PCI USB2.0 Controller

Revision 1.06, December 7, 2005

-15-

Function 2 Register Descriptions

Function 2 Device-Specific Registers

Offset 40 - Miscellaneous Control 1 (00h).......................RW

PCI Memory Command Option

0 Support “Memory Read Line”, “Memory Read

Multiple”,

and

“Memory

Write

and

Invalidate” commands............................default

1 Only supports “Memory Read” and “Memory

Write” commands

Babble Option

0 Auto-disable babbled port when EOF ...default

1 Keep babbled port enabled

PCI Parity Check

0 Disable ...................................................default

1 Enable

Reserved (Do Not Program) ................... default = 0

3-2

Reserved

........................................ always reads 0

DMA Options

0 8DW burst access...................................default

1 16DW burst access

PCI Wait States

0 Zero Wait States.....................................default

1 One Wait State

Offset 41 - Miscellaneous Control 2 (00h).......................RW

7-5

Reserved

........................................ always reads 0

Hold PCI REQ_ for successive access

0 Disable

1 Enable

3-0

Reserved

........................................ always reads 0

Offset 42 - Miscellaneous Control 3 (00h).......................RW

7-5

Reserved

........................................ always reads 0

Sub-system and sub-system Vendor ID R/W

0 Disable ...................................................default

1 Enable

3-0

Reserved

........................................ always reads 0

Offset 48 - Miscellaneous Control 4 (A0h) ......................RW

7-6

Reserved

........................................ always reads 0

Disable PCI burst access

0 Burst enable ...........................................default

1 Burst disable

4-0

Reserved

........................................ always reads 0

Offset 49 - Miscellaneous Control 5 (20h) ...................... RW

Enable MAC (provides more delay between

transactions)

0 Disable................................................... default

1 Enable

Enable MAC (provides timeout to device when

error is detected)

0 Disable................................................... default

1 Enable

Clock Auto Stop

0 Disable, no stop

1 Enable, auto stop ................................... default

4-0

Reserved

........................................always reads 0

Offset 4A - MAC inter-transaction delay parameter (00h)RO

Offset 4B - MAC turn around time parameter (09h).... RW

7-6

Reserved

........................................always reads 0

EHCI sleep time select

0 1 µs

.................................................... default

1 10 µs

Reserved

........................................always reads 0

3-0

USB 2.0 MAC TX time parameter .........default = 9

Offset 51 - USB 2.0 Timeout RX Parameter (5Ah) ....... RW

Offset 5B 5A - High-Speed Port Pad Termination Resistor

Fine Tune (4444h)............................................................. RW

15-12 Control A[3:0] ........................................default = 4h

11-8 Control B[3:0].........................................default = 4h

7-4

Control C[3:0] ........................................default = 4h

3-0

Control D[3:0] ........................................default = 4h

Offset 60 - Serial Bus Number (20h = USB 2.0) .............. RO

Offset 61- Frame Length Adjust (20h) ........................... RW

Offset 63-62 - Port Wake Capability (0001h)................. RW

Offset 83-80 - Power Management Capability................ RO

Function 0 49[1] = 0: ............................fixed at C9 C2 00 01h

Function 0 49[1] = 1: ............................ fixed at 48 0A 00 01h

Offset 84 - Power Mgmt Capability Status (00h or 03h) RW

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