VT6212 / VT6212L PCI USB2.0 Controller

Revision 1.06, December 7, 2005

-6-

Pin Descriptions

No Connection

Signal Name

Pin #

I/O

Power

Signal Description

NC

57-59, 97, 103-104

-

No connection.

USB Ports

Signal Name

Pin #

I/O

Power

Signal Description

USBP1+

86

IO

VCCUSB1

USB Port 1 Differential Data Plus. Asserted high (> 2.8V) †

USBP1–

85

IO

VCCUSB1

USB Port 1 Differential Data Minus. Asserted low (< 0.3V) †

USBP2+

82

IO

VCCUSB2

USB Port 2 Differential Data Plus. Asserted high (> 2.8V) †

USBP2–

81

IO

VCCUSB2

USB Port 2 Differential Data Minus. Asserted low (< 0.3V) †

USBP3+

78

IO

VCCUSB3

USB Port 3 Differential Data Plus. Asserted high (> 2.8V) †

USBP3–

77

IO

VCCUSB3

USB Port 3 Differential Data Minus. Asserted low (< 0.3V) †

USBP4+

74

IO

VCCUSB4

USB Port 4 Differential Data Plus. Asserted high (> 2.8V) †

USBP4–

73

IO

VCCUSB4

USB Port 4 Differential Data Minus. Asserted low (< 0.3V) †

USBOC1#

71

I

VCCSUS

USB Over-Current Input Port 1. When the supplied current exceeds 500 mA

on a USB port, USBOC# should be asserted. If this input is asserted low, the

host controller will disable USB port 1. The port will remain disabled as long

as the condition persists. See Design Guide and evaluation board schematics

for overcurrent detection scheme.

USBOC2#

68

I

VCCSUS

USB Over-Current Input Port 2. Same as above but for port 2.

USBOC3#

66

I

VCCSUS

USB Over-Current Input Port 3. Same as above but for port 2.

USBOC4#

65

I

VCCSUS

USB Over-Current Input Port 4. Same as above but for port 2.

XIN

94

I

VCCOSC

Crystal Input. May be connected to a 24 MHz parallel resonant fundamental

mode crystal (see Design Guide for specific connection details).

XOUT

95

O

VCCOSC

Crystal Output.

Must be connected to a 24 MHz parallel resonant

fundamental mode crystal (see Design Guide for specific connection details).

REXT

88

A

VCCPLL

External Resistor. Typical 6.12k

Ω 1% pull down to analog ground (see

Design Guide for specific connection details).

† Data encoding is NRZI (Non Return to Zero Inverted) so at times the reverse may be true (i.e., the plus pin may be asserted low

and the minus pin asserted high.)

Test Pins and Reserved Pins

Signal Name

Pin #

I/O

Power

Signal Description

ATPG_EN

63

I

VCC25

Automatic Test Program Generator Enable. Do not connect for normal

operation. Internal pulldown.

TESTMODE

64

I

VCC25

Test Mode Enable. Do not connect for normal operation. Internal pulldown.

TEST2

102

IO

VCC25

Test Signal 2. Leave unconnected for normal operation.

TEST3

99

IO

VCC25

Test Signal 3. Pull down 4.7K-ohm for normal operation.

WAKEUP_EN

98

IO

VCC25

WAKEUP_EN. Enable wakeup function