RT3662AC datasheet(23/37 Pages) RICHTEK

23 / 37 page

RT3662AC

is a registered trademark of Richtek Technology Corporation.

DS3662AC-00

March

2016

www.richtek.com

Application Information

Power Ready (POR) Detection

During start-up, the RT3662AC will detect the voltage

at the voltage input pins: VCC, PVCC and EN. When

VCC > 4.3V and PVCC > 3.85V, the IC will recognize

the power state of system to be ready (POR = high)

and wait for enable command at the EN pin. After POR

= high and VEN > 2V, the IC will enter start-up

sequence for both VDD and VDDNB rail. If the voltage

of VCC and EN pin drop below low threshold, the IC will

enter power down sequence and all the functions will

be disabled. Normally, connecting system power to the

EN pin is recommended. The SVID will be ready in 2ms

(max) after the chip has been enabled. All the

protection latches (OVP, OCP, UVP) will be cleared

only after POR = low. The condition of VEN = low will

not clear these latches.

Chip EN

POR

4.3V

3.85V

VCC

PVCC

CMP

Figure 1. Power Ready (POR) Detection

Boot VID

When EN goes high, both VDD and VDDNB output

begin to soft-start to the Boot VID in CCM. Table 7

shows the Boot VID setting. The Boot VID is

determined by the SVC and SVD input states at EN

rising edge and it is in the internal register. The digital

soft-start circuit ramps up the reference voltage at a

controlled slew rate to reduce inrush current during

start-up. When all the output voltages are above power

good threshold (300mV below Boot VID) at the end of

soft-start, the controller asserts power good (PGOOD)

after a time delay.

Table 7. 2-Bit Boot VID Code

Initial Startup VID (Boot VID)

SVC

SVD

VDD/VDDNB Output Voltage (V)

1.1

1.0

0.9

0.8

Start-Up Sequence

After EN goes high, the RT3662AC starts up and

operates according to the initial settings. Figure 2

shows the simplified sequence timing diagram. The

detailed operation is described in the following.

RT3662AC Datasheet(PDF) 23 Page - Richtek Technology Corporation

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